3.0 Registers
CX28394/28395/28398
3.13 Transmit Sa-Byte Buffers
Quad/x16/Octal—T1/E1/J1 Framers
3.13 Transmit Sa-Byte Buffers
Five transmit Sa-Byte buffers (TSA4–TSA8) are used to insert Sa-bits in TS0. The entire group of 40 bits is
sampled every 16 frames, coincident with the TMF interrupt boundary [addr 008]. Bit 0 from each TSA register
is then inserted during frame 1, Bit 1 during frame 3, Bit 2 during frame 5 and so on. This gives the processor up
to 2 ms after TMF interrupt to write new Sa-Byte buffer values. Transmit Sa-bits maintain a fixed relationship
to the transmit CRC multiframe.
07B—Transmit Sa4 Byte Buffer (TSA4)
7
6
5
4
3
2
1
0
TSA4[7]
TSA4[6]
TSA4[5]
TSA4[4]
TSA4[3]
TSA4[2]
TSA4[1]
TSA4[0]
TSA4[7]
Sa4 bit transmitted in frame 15
Sa4 bit transmitted in frame 13
Sa4 bit transmitted in frame 11
Sa4 bit transmitted in frame 9
Sa4 bit transmitted in frame 7
Sa4 bit transmitted in frame 5
Sa4 bit transmitted in frame 3
Sa4 bit transmitted in frame 1
TSA4[6]
TSA4[5]
TSA4[4]
TSA4[3]
TSA4[2]
TSA4[1]
TSA4[0]
07C—Transmit Sa5 Byte Buffer (TSA5)
7
6
5
4
3
2
1
0
TSA5[7]
TSA5[6]
TSA5[5]
TSA5[4]
TSA5[3]
TSA5[2]
TSA5[1]
TSA5[0]
TSA5[7]
Sa5 bit transmitted in frame 15
Sa5 bit transmitted in frame 13
Sa5 bit transmitted in frame 11
Sa5 bit transmitted in frame 9
Sa5 bit transmitted in frame 7
Sa5 bit transmitted in frame 5
Sa5 bit transmitted in frame 3
Sa5 bit transmitted in frame 1
TSA5[6]
TSA5[5]
TSA5[4]
TSA5[3]
TSA5[2]
TSA5[1]
TSA5[0]
3-68
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
