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CX28333-1X 参数 Datasheet PDF下载

CX28333-1X图片预览
型号: CX28333-1X
PDF下载: 下载PDF文件 查看货源
内容描述: 单/双/三E3 / DS3 / STS - 1线路接口单元 [Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit]
分类和应用: 电信集成电路PC
文件页数/大小: 68 页 / 549 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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1.0 Pin Description  
CX28331/CX28332/CX28333  
1.1 Pin Assignments  
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit  
Table 1-1. CX2833i-1x Pin Definitions (6 of 6)  
Pin #  
Signal Name  
Description  
I/O/P  
Notes  
CX28331-1x CX28332-1x CX28333-1x  
4, 5, 20, 21  
1, 8, 17, 24  
12, 13  
9, 16  
VDD  
VSS  
Power  
P
P
Connect to 3.3 V power.  
Connect to ground.  
Ground  
Miscellaneous  
Power down for Ch1  
58  
76  
25  
76  
58  
25  
PD  
PD1  
PD2  
PD3  
I
Power down transceiver channel  
0 = Power down channel (off)  
1 = Channel active (on)  
Note: A special power-down mode  
exists when all three PDBs are set  
low. This special mode shuts off the  
entire chip (including biasing). This  
is useful for static Idd testing.  
Power down for Ch2  
Power down for Ch3  
I
I
47  
65  
36  
65  
47  
36  
REFCLK  
REFCLK1  
REFCLK2  
REFCLK3  
Reference clock for Ch1  
I
Reference clock from off-chip.  
This clock should be set to one of  
the following:  
E3 rate (34.368 MHz)  
DS3 rate (44.736 MHz)  
STS-1 rate (51.84 MHz)  
Reference clock for Ch2  
Reference clock for Ch3  
I
I
The clock rate should correspond to  
the mode of operation that has been  
chosen for the channel.  
80  
80  
80  
RBIAS  
Bias resistor  
O
A 12.1 k± 1% resistor tied from  
this pin to ground provides the  
current reference to the entire  
chip.(2)  
78  
77  
78  
77  
78  
77  
Reset  
GPD  
Reset  
I/O Asynchronous reset (reset entire  
device).  
Global Power down  
I/O Power down (Static Idd testing).  
0 = Power down disable  
1 = Power down active  
2, 3, 6, 7, 18, 10, 11, 14,  
42  
NC  
No connect  
Not connected.  
19, 22, 23,  
25, 26, 27,  
29, 30, 31,  
32, 33, 34,  
35, 36, 37,  
38, 39, 40,  
42, 61, 62,  
63, 64, 65,  
66, 67, 68,  
69, 70, 71,  
72, 74, 75,  
76  
15, 42,  
4458  
NOTE(S):  
(1)  
This pin should be connected to 3.3 V in an all-3.3 V design.  
Placing a capacitor from this pin to ground may result in instabilities.  
(2)  
3. All digital input pins contain a 75 kpull-down resistor from input to DVSS.  
1-10  
Conexant  
100985A  
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