CX25870/871
1.0 Functional Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3 Device Description
Figure 1-22. FIELD Pin Output Timing Diagram (PAL-B, D, G, H, I, N, Nc)
RESET*
Start
of
VSYNC*
Analog
FIELD 1
Composite
Output
620
621
622
623
624
625
1
2
3
4
5
6
7
23
24
FIELD Pin
Output
Analog
FIELD 2
Composite
Output
308
309
310
311
312
313
314
315
316
317
318
319
320
336
337
FIELD Pin
Output
*FIELDI Bit = 0
100381_095
By default, the internal FIELDI bit will be 0 which forces the CX25870 to
transmit a logical 1 during transmission of an EVEN field and logical 0 for the
period of an ODD field. To change the FIELD polarity, reprogram the FIELDI bit.
If the CX25870/871 is the timing master and sends out HSYNC* and
VSYNC*, then after a power-on, pin, or timing reset (setting of bit 7, register
0x6C), the encoder and the flicker filter portions of the device start at line 1, pixel
1 of their respective timing generation. For the CX25870/871, this means the
ODD field is always the first field conveyed after a power-on reset, pin reset, or
timing reset.
When the CX25870 receives an interlaced data format, its FIELD pin
represents only the output field presently being generated by the on-chip DACs.
When the CX25870 receives progressive (i.e., noninterlaced) frames which have
no field associated with it, the CX25870’s input timing generator still keeps track
of frames received. As a result, after the entire second frame has been received,
the input and encoder sections become resynchronized. This re-synchronization is
done through an internal frame sync signal. This action, in turn, forces the
CX25870 to the beginning of the odd field and changes the FIELD pin back to its
odd state.
If the CX25870/871 is the timing slave (i.e., it accepts HSYNC* and
VSYNC*) receiving a power-on reset, pin reset, or timing reset (register 0x6C,
bit 7) causes the input timing generator to send the encoder the aforementioned
frame sync. This sets the encoder to the beginning of the odd field which is
denoted through the FIELD pin. The first digital HSYNC* and VSYNC*
combination then corresponds to the encoder’s EVEN output field. The second
digital HSYNC* and VSYNC* combination will again cause a frame sync and
the encoder will start sending the ODD field both from its DACs and FIELD pin.
This ODD–EVEN–ODD–EVEN … field sequence continues indefinitely.
100381B
Conexant
1-55
CONEXANT [ CONEXANT SYSTEMS, INC ]
