1.0 Functional Description
CX25870/871
1.3 Device Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3.13 RGB Inputs (For Standard TV Outputs)
With IN_MODE[3:0] set to a RGB mode, the encoder must receive digital
gamma-corrected RGB data as an input. If this occurs, the RGB data will be
converted to Y/R-Y/B-Y as follows:
Y[9:0] = [INT(0.299 * 210) * R[7:0]} + INT(0.587 * 210 * G[7:0] + INT(0.114 *
210) * B[7:0] + 27] * 2-8
0 ≤ Y[9:0] ≤ 1024
For 15 and 16 bit RGB input formats, individual R, G, and B values are left
justified to eight bit numbers.
After the initial conversion, the Y/R-Y/B-Y values are sub-sampled to 4:2:2
data prior to overscan compensation and flicker filtering.
The resulting 4:2:2 output must then be converted to YUV values and then
scaled for the output range of the DACs. The MY, MCR, and MCB registers must
be programmed to perform this conversion. The scaling equations are:
MY = (int)[V100/(255 * VFS)*26 + 0.5]
MCR = (int)[(128.0/127.0) * V100 * 0.877/(127 * VFS * sinx) * 25 + 0.5]
MCB = (int)[(128.0/127.0) * V100 * 0.493/(127 * VFS * sinx) * 25 + 0.5]
where:V100 = 100% white voltage (0.661 V for NTSC, 0.7 V for PAL)
VFS = Full scale output voltage (1.28 V)
Fsc = color subcarrier frequency (see Table A-2)
Fclk = CLKI input frequency
Sinx = Sin [(2π FSC/FCLK)/(2π FSC/FCLK)]
For SECAM formulas see the SECAM section.
1.3.14 Input Pixel Horizontal Sync
The HSYNC* pin provides line synchronization for the pixel input data. It is an
output in master interface and an input in slave and pseudo-master interface. In
the master interface, it is a pulse two CLKI cycles in duration whose leading edge
indicates the beginning of a new line of pixel data. The period between two
consecutive HSYNC* pulses is H_CLKI CLK cycles. The first active pixel
should be presented to the device H_BLANKI minus the internal pipelined clock
(5 CLK cycles) after the leading edge of HSYNC*. The next H_ACTIVE pixels
are accepted as active pixels and used in the construction of the output video. In
the slave interface the exact number of clocks per line (H_CLKI) must be
provided as calculated for the desired overscan ratio. Only the leading edge of
HSYNC* is used, low times must be at least two CLKI cycles in duration.
HSYNC* is clocked into the encoder by the rising edge of CLKI.
The polarity of the HSYNC* signal is changed by the HSYNCI register bit.
The default convention is active low.
1-30
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
