CX25870/871
1.0 Functional Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3 Device Description
1.3.15 Input Pixel Vertical Sync
The VSYNC* pin provides field synchronization for the pixel input data. It is an
output in master interface, and an input in the slave and the pseudo-master
interface.
For noninterlaced input timing in master interface, VSYNC* is a pulse one
horizontal line time in duration whose leading edge indicates the beginning of a
frame of input pixel data. The leading edge coincides with the leading edge of
HSYNC*. The period of the pulses is V_LINESI horizontal lines. The first line of
active data should be presented to the device V_BLANKI lines after the leading
edge of VSYNC*. The next V_ACTIVEI lines are accepted as active lines and
used in the construction of the output video.
The CX25870/871 disregards lines after the leading edge of VSYNC* but
before VSYNC* + V_BLANKI lines by not encoding them. In slave interface,
the period must be exactly the frame rate of the desired video format. Only the
leading edge is used, and the high and low duration must be at least two CLKI
cycles. The beginning of the frame of data is indicated by the next leading edge of
HSYNC* coincident with or after the leading edge of VSYNC*.
For interlaced input timing, only the slave interface is supported. The period
must be exactly the frame rate of the desired video format. If the leading edge of
HSYNC* and VSYNC* are coincident, that indicates the input is in odd field, the
internal line counter is reset to line 1 at the leading edge of VSYNC*. If the
leading edges of HSYNC* and VSYNC* are not coincident, and separated by a
minimum of two CLKI cycles, this indicates the input is an even field. In this
case, the internal line counter is reset to line 2 at the beginning of the next line.
Only the leading edge of VSYNC* is used, and the high and low VSYNC* width
must be at least two CLKI cycles. VSYNC* is clocked in by the rising edge of
CLKI.
The polarity of the VSYNC* input and output can be programmed by the
VSYNCI register bit. The default convention is active low. The FLD_MODE bits
allow further flexibility in HSYNC* and VSYNC* timing relationship.
1.3.16 Input Pixel Blanking
Input pixel blanking can be controlled by either the BLANK* pin or by the
internal registers. Blanking can be programmed independently of master or slave
interface using the EN_BLANKO register bit. As an output (EN_BLANKO = 1),
pixel blanking is generated based on the active area defined by H_BLANKI,
H_ACTIVE, V_BLANKI, and V_ACTIVEI registers. With EN_BLANKO = 1,
the BLANK* pin is output in the proper relationship to the syncs to indicate the
location of active pixels. As an input (EN_BLANKO = 0), when the BLANK* pin
goes high, it indicates the start of active pixels at the pixel input pins. In addition,
the H_BLANKI register must be programmed properly. The duration of active
data is still determined by the H_ACTIVE register. BLANK* is clocked by the
rising edge of CLKI.
An additional function for the BLANK* pin is used if the EN_DOT register
bit is set. If EN_DOT = 1, the BLANK* pin becomes an input whose rising edge
defines the graphics controller character clock boundary. This is used internally
by the encoder to keep track of the exact pixel count for controllers that cannot
operate at pixel clock rates but instead operate at VGA character clock rates.
The polarity of the BLANK* input/output can be programmed by the
BLANKI register bit. The default convention is active low.
100381B
Conexant
1-31
CONEXANT [ CONEXANT SYSTEMS, INC ]
