1.0 Functional Description
CX25870/871
1.1 Pin Descriptions
Flicker-Free Video Encoder with Ultrascale Technology
Table 1-1. Pin Assignments (3 of 3)
Pin Name
FIELD
I/O
Pin #
37
Description
O
Field control output (TTL compatible). FIELD transitions after the rising edge of
CLK, two clock cycles following falling HSYNC*. It is a logical 0 during odd
fields and is a logical 1 during even fields. If unused, FIELD should be left as a
no connect.
VSYNC*
HSYNC*
I/O
I/O
36
35
Vertical sync input/output (TTL compatible). As an output (timing master
operation), VSYNC* is output following the rising edge of CLK. As an input
(timing slave operation), VSYNC* is clocked on the rising edge of CLK.
Horizontal sync input/output (TTL compatible). As an output (timing master
operation), HSYNC* is output following the rising edge of CLK. As an input
(timing slave operation), HSYNC* is clocked on the rising edge of CLK.
P[23:21]
P[20:14]
P[13:0]
VSS
I
I
I
34-32
29-23
18-5
Pixel inputs. See Table 1-2. The input data is sampled on both the rising and
falling edge of CLK for multiplexed modes, and on the rising edge of CLK in
nonmultiplexed modes. A higher bit index corresponds to a greater bit
significance.
—
4, 21, 22,
31, 41
Digital ground for core logic. All AGND and VSS pins must be connected
together on the same PCB plane to prevent latchup.
XTL_BFO
O
3
Buffered crystal clock output. On power-up, the encoder will transmit a 0 to 3.3
V signal at a frequency equal to the frequency of the crystal found between the
XTALIN/XTALOUT ports. Normally the XTL_BFO output is at a rate of 13.500
MHz. If unused, XTL_BFO should be left as a no connect.
VDD
—
1, 2, 19,
20, 30,
60
Digital power for core logic. All VAA and VDD pins must be connected together
on the same PCB plane to prevent latchup.
1-4
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
