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CX20431-21 参数 Datasheet PDF下载

CX20431-21图片预览
型号: CX20431-21
PDF下载: 下载PDF文件 查看货源
内容描述: AccessRunner ADSL -USB调制解调器设备设置 [AccessRunner ADSL-USB Modem Device Set]
分类和应用: 调制解调器
文件页数/大小: 56 页 / 363 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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AccessRunner ADSL-USB Modem Device Set Data Sheet  
Table 3-1. P5200 UIC Hardware Signal Definitions (Continued)  
Label  
Pin  
I/O  
I/O Type  
Signal Name/Description  
CX11627 ADDP SERIAL CHANNEL INTERFACE  
Receive ATM0 Start of Cell. Connect to ADDP RXSOC0.  
Receive AS0/ATM0 Data Clock. Connect to ADDP R_CLK_LS0.  
Receive AS0/ATM0 Serial Data. Connect to ADDP R_DAT_LS0.  
Transmit ATM0 Start of Cell. Connect to ADDP TXSOC0.  
Transmit LS0/ATM0 Data Clock. Connect to ADDP T_CLK_LS0.  
Transmit LS0/ATM0 Serial Data. Connect to ADDP T_DAT_LS0.  
RXSOC0  
168  
169  
167  
173  
174  
170  
I
Itpu  
Itpu  
Itpu  
Otts4  
It  
RCLKAS0  
RDATAS0  
TXSOC0  
I
I
O
I
TCLKLS0  
TDATLS0  
O
Otts4  
CX20431 AFE AND CX20441 LD CONTROL  
AFE Reset. Active low reset output to the AFE and the LD. Connect  
to AFE POR# and to LD PWRDWN#.  
AFE_RST#  
(GPIO08)  
161  
166  
O
O
Ot4  
Line Driver Power Control. Optionally, connect to LD PWRDWN#  
LD_PC  
Ot4  
(GPIO13)  
when it is desired to power down only the LD.  
LINE INTERFACE  
Off-Hook Detect. Active low; indicates POTS off-hook event. Used  
for G.lite Mode only. Connect to off-hook detector circuit.  
LD_OH_DET  
(GPIO05)  
156  
3
I
It  
Inner/Outer Pair Select. Connect to wire-pair selection circuit.  
PAIR_SEL  
(GPIO21)  
O
O
Itpu/Ot4  
Itpu/Ot4  
Receive Pad. Connect to receive pad circuitry in hybrid.  
BCLKIO (GPIO38)  
30  
SERIAL EEPROM INTERFACE  
Serial EEROM Clock. Connect to EEPROM clock input.  
Serial EEROM Data. Connect to EEPROM data line.  
JTAG INTERFACE  
I2C_SCL (GPIO16)  
I2C_SDA (GPIO15)  
11  
12  
O
I
Ot4  
Itpu  
JTAG Reset. A high-to-low transition on this signal forces the TAP  
controller into a logic reset state. This pin has an internal pullup, and it  
conforms to IEEE 1149.1 JTAG specification.  
TRST#  
TCK  
TMS  
TDI  
31  
32  
33  
34  
35  
I
Itpu  
It  
JTAG Test Clock. This is the boundary scan clock input signal. This  
pin has an internal pullup, and it conforms to IEEE 1149.1 JTAG  
specification.  
I
JTAG Test Mode Select. This signal controls the operation of the  
TAP controller. This pin has an internal pull-up, and it conforms to  
IEEE 1149.1 JTAG specification.  
I
Itpu  
Itpu  
Otts4  
JTAG Test Input. This signal contains serial data that is shifted in on  
the rising edge of TCK. The pin has an internal pullup, and it conforms  
to IEEE 1149.1 JTAG specification.  
I
JTAG Test Output Data. This is the three-stateable boundary scan  
data output signal from the MCU, and it is shifted out on the falling  
edge of TCK. It conforms to IEEE 1149.1 JTAG specification.  
TDO  
O
Conexant  
100427B  
3-5  
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