5.0 Memory Organization
CN8478/CN8474A/CN8472A/CN8471A
5.1 Memory Architecture
Multichannel Synchronous Communications Controller (MUSYCC™)
The 1 MB memory ranges assigned to MUSYCC functions will not restrict
MUSYCC’s PCI interface from attempting to access these ranges. The host must
be cognizant that MUSYCC cannot respond to an access cycle which MUSYCC
itself initiates as the bus master.
Table 5-1. MUSYCC Register Map
Group
(Byte Offset from Base Address Register)
Register Map
0
1
2
3
4
5
6
7
Group Base Pointer
0000h
0800h
1000h
1800h
2000h
2800h
3000h
3800h
Dual Address Cycle Base Pointer(1)
Service Request Descriptor
00004h
0008h
0808h
1008h
1808h
2008h
2808h
3008h
3808h
Interrupt Status Descriptor(1)
Transmit Time Slot Map(2)
Transmit Subchannel Map(2)
000Ch
0200h
0280h
0380h
0A00h
0A80h
0B80h
1200h
1280h
1380h
1A00h
1A80h
1B80h
2200h
2280h
2380h
2A00h
2A80h
2B80h
3200h
3280h
3380h
3A00h
3A80h
3B80h
Transmit Channel Configuration
Table(2)
Receive Time Slot Map(2)
Receive Subchannel Map(2)
0400h
0480h
0580h
0C00h
0C80h
0D80h
1400h
1480h
1580h
1C00h
1C80h
1D80h
2400h
2480h
2580h
2C00h
2C80h
2D80h
3400h
3480h
3580h
3C00h
3C80h
3D80h
Receive Channel Configuration
Table(2)
Global Configuration Descriptor(1)
00600h
00604h
Interrupt Queue Descriptor(1)
Group Configuration Descriptor
Memory Protection Descriptor
Message Length Descriptor
Port Configuration Descriptor
060Ch
0610h
0614h
0618h
0E0Ch
0E10h
0E14h
0E18h
160Ch
1610h
1614h
1618h
1E0Ch
260Ch
2610h
2614h
2618h
2E0Ch
2E10h
2E14h
2E18h
360Ch
3610h
3614h
3618h
3E0Ch
3E10h
3E14h
3E18h
1E10h
1E14h
1E18h
Receive BIST Status(3)
Transmit BIST Status(3)
00640h
00644h
NOTE(S):
(1)
MUSYCC automatically maps Group 1 through 7 addresses for these registers to the Group 0 address (shown). For example,
accessing address 00E00h in MUSYCC (address for Group 1 Global Configuration register) automatically maps to address
00600h and the contents of 00600h is read or written.
The following descriptors are mapped to Internal RAM: Transmit Time Slot Map, Transmit Subchannel Map, Transmit
Channel Configuration Table, Receive Time Slot Map, Receive Subchannel Map, and Receive Configuration Table. Host must
not access internal RAM while channels are active. Updates to RAM must be performed via a service request.
The receive/transmit BIST diagnostic status registers.
(2)
(3)
5-4
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
