CN8478/CN8474A/CN8472A/CN8471A
5.0 Memory Organization
Multichannel Synchronous Communications Controller (MUSYCC™)
5.1 Memory Architecture
5.1.1 Register Map Access and Shared Memory Access
During MUSYCC’s PCI initialization, the system controller allocates a dedicated
1 MB memory range to each of MUSYCC’s PCI functions. The memory range
allocated to MUSYCC must not map to any other physical or shared memory.
Instead, the system configuration manager allocates a logical memory address
range, and notifies the system or bus controllers that any access to these ranges
must result in a PCI access cycle. MUSYCC is assigned these address ranges for
each function through the PCI configuration cycle. Once configured, MUSYCC
becomes a functional PCI device on the bus.
As the host accesses MUSYCC’s allocated address ranges, it initiates the
access cycles on the PCI bus. It is up to individual MUSYCC devices on the bus
to claim the access cycle. As its address ranges are accessed, MUSYCC behaves
as a PCI slave device while data is being read or written by the host. MUSYCC
responds to all access cycles where the upper 12 bits of a PCI address match the
upper 12 bits of either the EBUS Base Address register (Function 1) or the
MUSYCC Base Address register (Function 0).
For MUSYCC’s Function 1, a 1 MB memory space is assigned to the EBUS
Base Address register which is written into Function 1 PCI configuration space
(Table 2-14, Register 4, Address 10h). Devices connected to the EBUS can then
be allocated memory addresses within this 1 MB memory range. If MUSYCC
claims a PCI access cycle for Function 1, MUSYCC initiates EBUS arbitration
and ultimately accesses data from a device connected to the EBUS.
For MUSYCC’s Function 0, a 1 MB memory space is assigned to the
MUSYCC Base Address register which is written into Function 0 PCI
configuration space (Table 2-7, Register 4, Address 10h). Once a base address is
assigned to Function 0, a register map is used to access individual device resident
registers. The register map provides the byte offset from the Base Address register
where registers reside. The register map layout is listed in Table 5-1.
100660E
Conexant
5-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
