6.0 Basic Operation
CN8478/CN8474A/CN8472A/CN8471A
6.3 Channel Operation
Multichannel Synchronous Communications Controller (MUSYCC™)
GroupStr0.TxChannelConfigDescr[0] = 0x000024000;
/* for logical channel 1 */
/* everything same except as logical channel 0 */
/* buffer location index = 1 */
/* internal buffer length = 0 */
/* message length check register = 2, use register 2 */
GroupStr0.TxChannelConfigDescr[1] = 0x01002800;
/* for logical channel 2 */
/* everything same except as logical channel 0 */
/* buffer location index = 2 */
/* internal buffer length = 0 */
/* message length check register = 0, do not check */
GroupStr0.TxChannelConfigDescr[2] = 0x02002000;
/* either write directly into MUSYCC register - or - use a service request */
*(MUSYCC_FUNC_0_BAR + TX_CHANNEL_CONFIG_DESCR_OFFSET +0) =
GroupStr0.TxChannelConfigDescr[0];
*(MUSYCC_FUNC_0_BAR + TX_CHANNEL_CONFIG_DESCR_OFFSET +1) =
GroupStr0.TxChannelConfigDescr[1];
*(MUSYCC_FUNC_0_BAR + TX_CHANNEL_CONFIG_DESCR_OFFSET +2) =
GroupStr0.TxChannelConfigDescr[2];
The components of the Channel Configuration Descriptor are listed in Table 6-10.
Table 6-10. Example—Components of Channel Configuration Descriptor
Component of
Descriptor
Descriptor
Value of Components
0 = Pad count adjustment disabled
Transmit
Channel
Configuration
Descriptor
PADJ
BUFFLOC
0 = For logical channel 0
1 = For logical channel 1
2 = For logical channel 2
INV
0 = Data inversion disabled
BUFFLEN
EOPI
0 = Total FIFO = (0+1)*2 = 2 dwords
0 = End-of-padfill interrupt disabled
2 = HDLC w/ 16-bit FC
PROTOCOL
MAXSEL
1 = For logical channel 0 application
2 = For logical channel 1 application
0 = For logical channel 2 application
FCS
0 = FCS transfer normal
MSKSUERR
MSKSINC
MSKSDEC
MSKSFILT
MSKIDLE
MSKMSG
MSKEOM
MSKBUFF
0 = Interrupt masking disabled therefore enabling these interrupts
6-18
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
