5.0 Memory Organization
CN8478/CN8474A/CN8472A/CN8471A
5.2 Descriptors
Multichannel Synchronous Communications Controller (MUSYCC™)
Table 5-9. Service Request Descriptor (1 of 2)
Bit
Field
Name
Value
Description
31:13
12:8
RSVD
0
0
Reserved.
SREQ[4:0]
No Operation. This service request performs no action other than to facilitate a
Service Request Acknowledge Interrupt (SACK). This would be used as a “UNIX
ping-like” operation to detect the presence of a channel group processor.
1
2
Soft Chip Reset. This is identical to a hardware reset. Set PORTMAP = 0, disable all
supported ports (both directions), and deactivate all 32 channels of all supported
groups (both directions). The Interrupt Status Descriptor is reset to point to the first
dword in the queue, and all indicator bits are reset.
This service request is not acknowledged by MUSYCC.
Soft Group Reset. This is similar to a hardware reset for a specified group and
direction. Disable all specified ports (both directions), and deactivate all 32 channels
of specified group (both directions).
3
4
Reserved.
Global Initialization. For the entire device, read the Global Configuration Descriptor
and the Interrupt Queue Descriptor from shared memory. This initialization is
performed following a hardware or soft-chip reset. The Interrupt Status Descriptor is
reset to point to the first dword in the queue, and all indicator bits are reset.
5
Group Initialization. For this group and direction, read the following from shared
memory:
Time Slot Map
Subchannel Map
Channel Configuration Descriptor
Group Configuration Descriptor
Memory Protection Descriptor
Message Length Descriptor
Port Configuration Descriptor
This initialization must be performed by the host driver for each group and each
direction immediately following any reset or global initialization.(1)
5-14
Conexant
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CONEXANT [ CONEXANT SYSTEMS, INC ]
