2.0 Host Interface
CN8478/CN8474A/CN8472A/CN8471A
2.2 PCI Configuration Registers
Multichannel Synchronous Communications Controller (MUSYCC™)
Register 0, Address 00h
Table 2-10. Register 0, Address 00h
Bit
Reset
Value
Name
Field
Type
Description
Device ID(1)
31:16
15:0
847xh
RO
This unique device identification is assigned by the
manufacturer. This field always returns the value 847xh where x
can be 1, 2, 4, or 8 depending on the 32, 64, 128, or 256 channel
version of the device, respectively.
Vendor ID(1)
14F1h
RO
The unique vendor identification assigned to the manufacturer.
This field always returns the value 14F1h.
NOTE(S):
(1)
Registers shared between Function 0 and 1.
Register 1, Address 04h
The Status register records status information for PCI bus-related events. The
Command register provides coarse control to generate and respond to PCI
commands.
At reset, MUSYCC sets the bits in this register to 0. This means MUSYCC is
logically disconnected from the PCI bus for all cycle types except configuration
read and configuration write cycles.
Table 2-11. Register 1, Address 04h (1 of 2)
Bit
Field
Reset
Value
Name
Type
Description
31
Status
0
RR
Detected parity error. This bit is set by MUSYCC whenever it
detects a parity error on a data phase.
30
29
0
0
RO
RO
RO
RO
RO
Unused.
Unused.
Unused.
Unused.
28
0
27
0
26:25
01b
DEVSEL* timing. Indicates MUSYCC is a medium-speed device.
This means the longest time it will take MUSYCC to return
DEVSEL* when the EBUS is the target is 3 clock cycles.
24
23
0
RO
RO
Unused.
01b
Fast back-to-back capable. Indicates that when the EBUS is a
target, it is capable of accepting fast back-to-back transactions
when the transactions are not to the same agent.
22
21
0
RO
RO
Unused.
01b
Indicates the device is 66 MHz capable. This bit is set by
Revision C and later devices.
20:16
0
RO
Unused.
2-14
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
