2.0 Host Interface
CN8478/CN8474A/CN8472A/CN8471A
2.2 PCI Configuration Registers
Multichannel Synchronous Communications Controller (MUSYCC™)
2.2.5 PCI Bus Parity
The agent driving the AD[31:0] signals during any bus phase must also drive the
even parity signal (PAR). PAR is driven one clock after AD[31:0] has been driven
as follows:
•
•
•
Address phase: master always drives PAR one clock after address phase.
Read data phase: target always drives PAR one clock after read data phase.
Write data phase: master always drives PAR one clock after write data
phase.
PAR provides even parity across the AD[31:0] and CBE[3:0]* signal lines.
The agent receiving the data must assert PERR* if it detects a parity error,
provided its Parity Error Response enable bit is set.
If a parity error occurs, the master that generated the cycle (whether it asserted
PERR* or detected it) reports parity errors to the host. MUSYCC does this by
generating an Interrupt Descriptor. It also sets the Data Parity Detected bit (for
masters only) in the Status register in the appropriate function’s PCI configuration
space and sets the Detected Parity Error (for masters or targets) in the same
register if MUSYCC is the agent that detected the error.
PERR* reports errors on the data phases. MUSYCC not only asserts PERR*
when appropriate, but monitors PERR* for its own memory transactions and
notifies the host of the parity error.
SERR* reports parity errors on the address phases. It is assumed that this open
drain PCI signal is tied directly to the host’s system error pin. MUSYCC does not
generate an Interrupt Descriptor if it detects a parity error on an address phase,
nor does it respond to SERR* assertion.
2.2.6 PCI Throughput and Latency Considerations
In PCI systems, achieving high bus throughput works against achieving low bus
latency. As devices burst more data, they keep the bus longer, causing other
devices waiting for the bus to experience a longer acquisition latency as a result.
A PCI bus master introduces latency each time it uses the PCI bus to perform
a transaction. The bus master latency is a function of the following:
•
•
Behavior of the master
– State of the GNT* signal
– Bus command used (read, write,...)
– Burst length
– Master data latency for each data phase
– Value of Latency Timer
Behavior of the target
– Bus command used (read, write,...)
– Target latency
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