3.0 Digital Processing and Functionality
3.2 Effects
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
The ECCGATE register bit must be 1 for normal operation. When this bit is
set to 1, current data is displayed for one frame, and then the NULL data
sequence is displayed until new data is written to the registers. If ECCGATE is set
to 0, old data is displayed until new data is written to the registers.
Register bits CC_STAT (01[0]) and XDS_STAT (01[1]) allow monitoring of
data latching and encoding. When CC data is latched into the Bt861 registers, the
CC_STAT register bit is set to 1; when the data is encoded, it is set to 0. When
XDS data is latched into the Bt861 registers, the XDS_STAT register bit is set
to 1; when the data is encoded, it is set to 0.
By default, the CC or XDS waveform is placed at an appropriate start point
and has a data frequency of 503.4965 kb/s, however, both the start point and
signal width can be modified using registers fields CCSTART and CC_ADD,
respectively. Figure 3-20 illustrates a typical CC or XDS waveform. The
waveform consists of a clock run-in, a start bit, and two bytes of data, which is
encoded LSB first. The Bt860/861 automatically creates the clock run-in and start
bit, but does not calculate the parity bits. CC and XDS use an NRZ waveform,
where a logical 0 is represented by a black, and a logical 1 is represented as 50
IRE. Pixel data is ignored during active CC and XDS lines, but the CC or XDS
waveforms will be overwritten by Teletext data when Teletext is active on the CC
or XDS line.
Figure 3-20. Closed Captioning or Extended Data Service Waveform (Null Sequence)
MSB Byte 1
MSB Byte 2
50 IRE
Byte 1
Byte 2
Clock
2 Bytes of Data
Run-in
Start
Bit
861_014
3.2.18.1 Closed
Captioning Pass-through
There is no explicit means for accepting broadband vertical blanking interval
(VBI) content through the data port. However, by expanding the active video
region to include the CC line, the device can encode this data properly for output.
3-30
Conexant
D860DSA