3.0 Digital Processing and Functionality
3.1 Video
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Figure 3-2. PAL Vertical Timing
(1)
Odd Field
Even Field
861_033
O
V
NOTE(S):
(1)
Internal timing considers this point the start of the field (vertical reset).
3.1.4 Analog Video Blanking
In master mode, and when register bit BLK_IGNORE = 1 in slave mode, register
fields HBLANK, VBLANK, HACTIVE, and VACTIVE control analog video
blanking. Together they define the active region, where pixels will be displayed.
VBLANK defines the number of lines from the leading edge of the analog
vertical sync (O ) to the first active line (see Figures 3-1 and 3-2). VACTIVE
v
defines the number of active lines. HBLANK defines the number of system
clocks (minus 14) from the leading edge of horizontal sync to the first active
pixel. HACTIVE defines the number of active pixels per line.
In the slave mode, when BLK_IGNORE = 0, the BLANK* pin determines
analog blanking. The video from the start of horizontal sync through the end of
the burst, as well as the vertical lines with serration and equalization pulses is
automatically blanked.
3-10
Conexant
D860DSA
CONEXANT [ CONEXANT SYSTEMS, INC ]
