Bt860/861
3.0 Digital Processing and Functionality
3.1 Video
Multiport YCrCb to NTSC/PAL /SECAM
3.1Video
3.1.2 Analog Horizontal Sync
The duration of the horizontal sync pulse is determined by register
HSYNC_WIDTH (12[7:0]). The beginning of the horizontal sync pulse
corresponds to the reset of the internal horizontal pixel counter. The sync rise and
fall times are automatically controlled. The horizontal and vertical sync
amplitude is programmable using register SYNC_AMP (IE[7:0]).
3.1.3 Analog and Digital Vertical Sync
The duration of the analog and digital vertical sync is determined by register bit
VSYNC_DUR (16[6]). If VSYNC_DUR = 0, 3.0 lines are selected; if
VSYNC_DUR = 1, 2.5 lines are selected. Tables 3-2, 3-3, and 3-4 list the
appropriate VSYNC_DUR settings for all supported standards.
Figures 3-1 and 3-2 illustrate 3.0 and 2.5 lines respectively.
Figure 3-1. NTSC Vertical Timing
(1)
O
Odd Field
V
Even Field
NOTE(S):
(1)
Internal timing considers this point the start of the field (vertical reset).
861_032
D860DSA
Conexant
3-9
CONEXANT [ CONEXANT SYSTEMS, INC ]
