Bt860/861
2.0 Inputs and Timing
Multiport YCrCb to NTSC/PAL /SECAM
2.3 Configurations and Timing
Figure 2-9. Video Decoder Connection Example
Bt835 Video Decoder
Bt860/861
8
VD[15:8]
CLKX2
VALID
ACTIVE
VACTIVE
FIELD
VID[7:0]
VIDCLK
VIDVALID
VIDHACT
VIDVACT
VIDFIELD
MPEG-2 Decoder
8
P[7:0]
CLKO
HSYNC*
VSYNC*
FIELD
Graphic Processor
8
2
OSD[7:0]
ALPHA[1:0]
XTI
XTO
861_008
Follow these steps to lock a video decoder to this port:
1. Connect to the data and control pins as illustrated in Figure 2-9.
2. Select the correct effective clock frequency using the PLL_FRACT and
PLL_INT registers, and choose the XTAL inputs as the system clock
source using register bit PCLK_SEL (19[7]). See Section 2.4.1, and the
PLL_FRACT and PLL_INT register descriptions.
3. Set these locking registers to the following values:
FIELD NAME
XL_MDSEL[1:0]
XL_SATEN
VALUE
11
1
XL_SAT[3:0]
1
4. Set the part for Timing Mode 1 (see Table 2-2).
5. Initiate locking by setting the LOCK (1C[5]) register bit high and the
LC_RST (1C[6]) register bit low.
NOTE: When unlocking the Bt861 to a source on the VID port, set the
LOCK (1C[5]) register bit low and the LC_RST (1C[6]) register bit high.
D860DSA
Conexant
2-13
CONEXANT [ CONEXANT SYSTEMS, INC ]
