2.0 Inputs and Timing
2.4 Clock Selection
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
2.4 Clock Selection
The internal pixel clock (PCLK) can be derived from either the CLKIN input or
the crystal inputs. The PCLK_SEL register bit (19[7]) controls which of these
two inputs will become the pixel clock.
2.4.1 Crystal Inputs and the PLL
The crystal inputs (XTI and XTO) drive a buffered oscillator to create a clock.
This clock is routed through the PLL if register bit BY_PLL (1D[3]) is 0, and
bypasses the PLL untouched if BY_PLL is 1. Figure 2-10 illustrates the clock
block diagram. If PCLK_SEL is low, this becomes the system clock.
The PLL_FRACT and the PLL_INT registers determine the PLL clock
frequency multiplier. The default setting generates a 27.0 MHz clock, using a
14.31818 MHz crystal.
If the VID port is enabled using the LOCK (1C[5]) register bit, the PLL is
controlled by the tracking servo mechanism.
The frequency programmed through PLL_FRACT and PLL_INT is used as a
base around which the VID port locking mechanism adjusts the system clock.
The PLL_FRACT and PLL_INT registers remain unaffected by the locking
mechanism, and when locking is disabled (through the LOCK bit), the
PLL_FRACT and PLL_INT registers once again determine the exact PLL
frequency.
Figure 2-10. Timing and Clock Block Diagram
8
OSD[7:0]
P[7:0]
OSD[7:0]
P[7:0]
8
VID[7:0]
CCIR656
Timing
Translator
3
8
System
Block
Encoder
Timing
Block
1
0
3
3
HSYNC*
VSYNC*
BLANK*
EN_656
PCLK_SEL
SLAVE
System
Clock
1
0
CLKIN
1
0
Xtal
Inverter
and Buffer
XTI
XTO
PLL
CLKO_DIS
BY_PLL
CLKO
VIDCLK
VID[7:0]
8
8
FIFO
861_025
2-14
Conexant
D860DSA
CONEXANT [ CONEXANT SYSTEMS, INC ]
