Bt860/861
2.0 Inputs and Timing
Multiport YCrCb to NTSC/PAL /SECAM
2.3 Configurations and Timing
If the registers are used to determine video blanking (register bit
BLK_IGNORE = 1), the first component of the first active pixel of a line should
be presented to the encoder at HBLANK + 2 rising system clock edges after the
falling edge of HSYNC* for master mode, and HBLANK + 3 rising system clock
edges after the falling edge of HSYNC* for slave mode. The correct order of the
pixel components is Cb , Y , Cr , Y , Cb , Y , Cr .... Figure 2-5 illustrates this
0
0
0
1
2
2
2
timing relationship.
Figure 2-5. Pixel Timing for Timing Modes 1 and 2
(1)
1
t
(2)
2
t
Video Out
(3)
3
t
Pixel
Data
Cb
Y
Cr
Y
Cb
Y
Cr
2
0
0
0
1
2
2
(4)
4
t
System
Clock
(5)
HSYNC*
BLANK*
t
5
NOTE(S):
(1)
Blanking times (t ) are listed in Tables 3-1 through 3-4. Desired front porch blanking is set by the HBLANK register.
1
HBLANK = t + 14
1
(2)
(3)
(4)
The number of active pixels per line (t ) is set by the HACTIVE register.
The total number of system clocks per line (t ) is set by the HCLK register.
The first component of the first active pixel of the line should be placed HBLANK + 2 (or 3 for slave mode) rising system
2
3
clock edges after falling HSYNC*(t ) in order to coincide with the end of horizontal blanking.
When the BLANK* pin is used, the first component of the first pixel must arrive 3 rising system clock edges after the
4
(5)
falling edge of BLANK* (t ).
5
861_006
If the BLANK* signal is used to determine video blanking (in slave mode
only), the first component of the first active pixel of a line should be presented to
the encoder three rising system clock edges after the falling edge of the BLANK*
signal. Figure 2-5 illustrates this relationship.
D860DSA
Conexant
2-9
CONEXANT [ CONEXANT SYSTEMS, INC ]
