Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
3.16 Data Link Registers
PRM_CR
PRM_R
Transmit CR Message Bit—The processor writes the selected C/R bit value to send in each PRM.
Transmit R Message Bit—The processor writes the selected R bit value to send in each PRM.
Transmit U1 Message Bit—The processor writes the selected U1 bit value to send in each PRM.
Transmit U2 Message Bit—The processor writes the selected U2 bit value to send in each PRM.
Transmit SL Message Bit—The processor writes the selected SL bit value to send in each PRM.
PRM_U1
PRM_U2
PRM_SL
AUTO_SL
Automatic SL Bit Insertion—RFSLIP error status is encoded into the transmit PRM contents,
or the PRM_SL bit value supplied by the processor is sent.
0 = send PRM_SL value in SL bit
1 = send RFSLIP error status in SL bit
SEND_PRM
Immediately Generate and Send PRM—Similar to AUTO_PRM mode, SEND_PRM instructs
the data link transmitter to format and send a Performance Report Message according to ANSI
T1.403-1995. SEND_PRM executes immediately rather than waiting for an ONESEC
interrupt. Thus, SEND_PRM gives processor control over PRM transmit timing. This is easier
for the processor to manage if other FDL message types must also be transmitted.
0AB—TDL #1 FIFO Empty Control (TDL1_FEC)
7
6
5
4
3
2
1
0
—
—
FEC[5]
FEC[4]
FEC[3]
FEC[2]
FEC[1]
FEC[0]
FEC[5:0]
Near Empty Transmit FIFO Threshold—Selects FIFO depth of near empty interrupt [TNEAR;
addr 009] and near empty level status [TNEAR1; addr 0AE]. The TNEAR interrupt is
activated when the number of data bytes remaining to be transmitted from the FIFO falls below
the selected threshold. The TNEAR1 indicator is active as long as the number of
processor-filled FIFO locations is below the selected threshold. Thus, TNEAR1 is active-high
when the transmit FIFO is empty, and remains active until the processor writes the selected
threshold number of bytes to TDL1 [addr 0AD]. Assuming the processor writes 64 bytes to fill
an empty FIFO, a TNEAR interrupt occurs after the transmitter has sent the number of bytes
required to bring the FIFO level back down below the selected threshold. Hence, the processor
can consecutively write 64 - FEC[5:0] number of bytes to the transmit FIFO in response to a
TNEAR interrupt. The interrupt also signifies time remaining (in bytes) for the processor to
write TDL1 before transmit FIFO is emptied. Typically, FEC[5:0] is set to a small value
(below 10-byte threshold) to minimize the number of TNEAR interrupts and maximize the
time between TNEAR interrupts.
FEC[5:0]
00 0000
00 0001
00 0010
|
Byte threshold @ TNEAR
disabled
Empty @ TNEAR
disabled
63 empty
62 empty
|
1 byte threshold
2 byte threshold
|
11 1110
11 1111
62 byte threshold
63 byte threshold
2 empty
1 empty
N8370DSE
Conexant
3-99
CONEXANT [ CONEXANT SYSTEMS, INC ]
