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BT8375EPF 参数 Datasheet PDF下载

BT8375EPF图片预览
型号: BT8375EPF
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片收发器T1 / E1和综合业务数字网( ISDN )基本速率接口 [single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces]
分类和应用: 电信集成电路综合业务数字网
文件页数/大小: 323 页 / 1950 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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Bt8370/8375/8376  
Fully Integrated T1/E1 Framer and Line Interface  
3.16 Data Link Registers  
Abort status is reported if the receiver detects a string of 7 or more consecutive 1s during an  
HDLC message. FCS error status is reported if FCS mode is enabled, and the checksum  
calculated over the received HDLC message does not match the received 16-bit FCS.  
Non-integer error status is reported if the receiver detects a closing FLAG character that yields  
an HDLC message length that is not an integer number of 8-bit octets.  
00 = Good  
01 = FCS/Non-integer  
10 = Abort  
11 = Partial  
RDL1_CNT[5:0]  
Byte Count [5:0]Indicates the number of Message Data [WORD1] bytes stored in  
subsequent consecutive FIFO locations and which constitute one received message. The  
reported byte count is the actual number of bytes, from 0 to 63 bytes, where 0 indicates 0 bytes  
for the processor to read. The processor can either read the specified number of message data  
bytes consecutively from RDL1, or poll RDL1_STAT after reading each data byte until  
RDL1_STAT reports an end of message (i.e., RMPTY1=1 or RSTAT1=1).  
WORD1: Message Data  
7
6
5
4
3
2
1
0
RDL1[7]  
RDL1[6]  
RDL1[5]  
RDL1[4]  
RDL1[3]  
RDL1[2]  
RDL1[1]  
RDL1[0]  
RDL1[7:0]  
Receive Message DataFilled by the receiver data link, from LSB to MSB, with bits from the  
selected channel. The processor reads 8-bit FIFO data during HDLC and Pack8 modes. During  
Pack6 mode, only the six least significant bits RDL1[5:0] are filled.  
0A9RDL #1 Status (RDL1_STAT)  
7
6
5
4
3
2
1
0
RMSG1  
RSTAT1  
RMPTY1  
RNEAR1  
RFULL1  
RMSG1  
In-Progress Receive MessageReal time status of receive message sequencer is provided  
mostly for processor-polled applications. During HDLC modes, RMSG1 is high for the  
interval between opening and closing FLAG characters to indicate that the receiver is filling  
FIFO locations (in which case RSTAT1 is also held high). RMSG1 is low while the channel  
receives FLAG or abort characters. During unformatted modes, RMSG1 is high continuously.  
0 = channel idle  
1 = channel actively filling FIFO  
RSTAT1  
Next, FIFO Read Equals Message StatusFor non-empty FIFO conditions (RMPTY1=0),  
RSTAT1 indicates that the next byte read from RDL1 returns WORD0 message status or  
WORD1 message data. RSTAT1 equals zero if the FIFO is empty and no message is  
in-progress. The processor polls RSTAT1 before reading RDL1 to determine how to interpret  
RDL1 read byte value, or the processor checks RSTAT1 in response to RMSG interrupt [ISR2;  
addr 009].  
0 = RDL1 byte equals Message Data (or empty FIFO, if RMTPY1=1)  
1 = RDL1 byte equals Message Status (if RMPTY1=0)  
N8370DSE  
Conexant  
3-97