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BT8375EPF 参数 Datasheet PDF下载

BT8375EPF图片预览
型号: BT8375EPF
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片收发器T1 / E1和综合业务数字网( ISDN )基本速率接口 [single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces]
分类和应用: 电信集成电路综合业务数字网
文件页数/大小: 323 页 / 1950 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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Bt8370/8375/8376  
Fully Integrated T1/E1 Framer and Line Interface  
3.7 Receive LIU Registers  
BPV  
Bipolar ViolationReports one or more bipolar violations detected on RTIP/RRING data  
inputs. Depending on RZCS [addr 040], the BPV may include bipolar violations received as  
part of a B8ZS or HDB3 0 code substitution. Detection of BPV or LCV errors can be selected,  
regardless of whether or not receive ZCS decoding is enabled [RAMI; addr 040]. BPV is  
latched active high upon detection of the first error. The active high hold interval is defined by  
LATCH_ERR [addr 046]. BPV errors are also accumulated in LCV count [addr 054, 055].  
BPV  
T1/E1N RZCS  
BPV Status  
0
1
1
X
0
X
0
No error  
All BPVs, including HDB3 coded BPV  
0
1
Code violation per ITU 0.162 (two consecutive BPVs of  
same polarity)  
1
1
1
1
0
1
All BPVs, including B8ZS coded BPV  
Only BPVs that are not part of B8ZS  
EYEOPEN  
PRE_EQ  
Equalization StateEYE OPEN indicates the real-time status of RLIU adaptive equalizer, and  
is intended only for diagnostic testing. Remains active as long as a valid receive AMI signal is  
present on RTIP/RRING. When SQUELCH [addr 020] is enabled and EYEOPEN status is 0,  
RLIU data outputs are forced to 0.  
0= Indicates the received signal is not valid.  
1= Indicates the received signal is valid and the RPLL is locked.  
Pre-Equalizer status. Indicates whether the pre-equalizer is enabled (on) or disabled (off).  
0= PRE_EQ is off  
1= PRE_EQ is on  
See PRE_EQ register [addr 02A]  
022Receive LIU Configuration (RLIU_CR)  
7
6
5
4
3
2
1
0
FRZ_SHORT  
HI_CSLICE  
AGC[1]  
AGC[0]  
EQ_FRZ  
OOR_BLOCK  
RLB0  
LONG_EYE  
FRZ_SHORT  
Freeze equalizer for short linesWhen set, the equalizer is not updated when the received  
signal is approximately 15 dB or larger.  
0 = equalizer updates for all lines  
1 = enable equalizer freezing if short line  
HI_CSLICE  
AGC[1:0]  
High Clock Slicer Threshold.  
0 = normal operation  
AGC Observation WindowSet to 0x11 for normal operation. Determines the period, in bit  
times, for Automatic Gain Control updates.  
00 = 32 bits  
01 = 128 bits  
10 = 512 bits  
11 = 2048 bits  
EQ_FRZ  
Freeze EQ Coefficients.  
0 = normal operation, equalizer always updates depending on  
FRZ_SHORT setting  
1 = freeze coefficients, equalizer does not update. Does not affect AGC  
operation  
N8370DSE  
Conexant  
3-41  
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