Bt8370/8375/8376
3.0 Registers
Fully Integrated T1/E1 Framer and Line Interface
3.4 Interrupt Status Registers
00A—Data Link 2 Interrupt Status (ISR1)
All events in ISR1 are from rising edge sources. Each event is latched active-high and held until the processor
read clears ISR1. Each event triggers an interrupt if the corresponding IER1 bit is enabled [addr 012].
For Bt8370 and Bt8375
7
6
5
4
3
2
1
0
RBOP
RFULL2
RNEAR2
RMSG2
TDLERR2
TEMPTY2
TNEAR2
TMSG2
For Bt8376
7
6
5
4
3
2
1
0
RBOP
—
—
—
—
—
—
—
RBOP
BOP Codeword Received—Set when a valid Bit Oriented Codeword is received and available
in the RBOP register [addr 0A2].
RFULL2
Receive FIFO Full—In HDLC modes, RFULL is set when the data link receiver attempts to
write received data to a full FIFO causing the receive data link FIFO to overrun. In
unformatted modes (Pack6 and Pack8), RFULL is set when the receive FIFO is filled to the
MSG_FILL limit selected in register RDL2_FFC [addr 0B2].
RNEAR2
RMSG2
Receive FIFO Near Full—Set when the receive FIFO fill level reaches the near full threshold
selected in register RDL2_FFC [addr 0B2].
Message Received—Set when a complete message or a partial message is received and
available in the receiver FIFO.
TDLERR2
Transmit FIFO Error—Set when the FIFO underruns as a result of the internal logic emptying
the FIFO without encountering an end of message [TDL2_EOM; addr 0B7]. The underrun
condition also forces transmission of an HDLC abort code.
TEMPTY2
TNEAR2
TMSG2
Transmit FIFO Empty—Set when the FIFO overflows as a result of the processor attempting to
write to a full FIFO. Overflow data is ignored by the transmit FIFO.
Transmit FIFO Near Empty—Set when the transmit FIFO level falls below the threshold
selected in register TDL2_FEC [addr 0B6].
Message Transmitted—Set when a complete message has been transmitted and the closing flag
is just beginning transmission.
N8370DSE
Conexant
3-21
CONEXANT [ CONEXANT SYSTEMS, INC ]
