2.0 Functional Description
CN8223
2.6 ATM Cell Processing
ATM Transmitter/Receiver with UTOPIA Interface
.
Segment Type
BOM or COM
EOM
Payload Length
44
4–44 mod 4
8–44 mod 4
SSM
Errors are counted in the PAY_LEN_ERR counter [0x4C] and indicated in
EVENT_STATUS. No payload length checking is performed on cells
matching the idle header description.
All errors disabled by the global disables in CELL_VAL are counted, and the
first enabled error in the above sequence of checks is counted in the appropriate
cell error counter. Disabled errors will not cause the cell to be marked as invalid.
Header octets are compared to the HDR_VAL registers under control of the
HDR_MSK bits. This determines routing to the proper output port. If no match is
made to any of the VCI/VPI fields for the four ports or to the idle definition, the
cell is counted in the NON_MATCH_CNT counter [0x57]. Payload CRC-10 and
length checks can also be disabled on a per port basis by using the control bits in
CONFIG_4. These bits simply disable the error from marking the cell as invalid
and do not affect the counting of errors in any way. This feature can be used to
route AAL 3/4 cells to one port with checks enabled and AAL5 cells to a different
port with checks disabled.
HEC Coverage [bit 1] in CONFIG_3 determines the calculation range for the
HEC. If this bit is low, the HEC is calculated over header octets 1–4 for ATM
cells. If this bit is high, the HEC is calculated over header octets 2–4 for
SMDS/802.6 cells.
Validation checks can be individually disabled with the remaining control bits
in the CELL_VAL register [0x14]. Disable HEC Check [bit 9] disables the check
of the header error control octet. Disable Payload Length Check [bit 10] disables
the check for consistency between the segment type field and the length field.
Disable Payload CRC Check [bit 11] disables the check of the payload CRC. The
above disables are global disables for all ports and override the per-port control in
CONFIG_4, which also contains per port disables for payload length and payload
CRC checks.
2.6.2.3 Interrupts and
Status Counters for Cell
Validation
Cell error events are indicated with bits 0–6 of the EVENT_STATUS register
[0x39] and can cause an interrupt if enabled with the corresponding bit in the
EN_EVENT_INT register [0x2E]. Status bits are latched at the event occurrence
and are cleared when EVENT_STATUS is read. The error events are also
counted, and interrupts on error counter overflows can be enabled in
EN_OVFL_INT [0x2F]. Counter overflow status is provided in OVFL_STATUS
[0x3A], and the status bits are cleared when the status register is read. These
counters are not latched, and each counter is cleared individually when it is read.
CELL_RCV_CNTx [0x52–0x55] provides a count of all cells that are
accepted for processing and delivery to Port x. This count is based on a header
match with the header value and mask bits that are set in the associated registers
for Port x. This count does not include cells discarded due to an error in the HEC.
IDLE_CELL_CNT [0x56] is a count of valid cells received that match the
programmed idle value and mask. NON_MATCH_CNT [0x57] is a count of
active cells that did not match any of the programmed VCI/VPI values (port or
idle).
2-32
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
