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28222-13 参数 Datasheet PDF下载

28222-13图片预览
型号: 28222-13
PDF下载: 下载PDF文件 查看货源
内容描述: ATM发射器/接收器与UTOPIA接口 [ATM Transmitter/Receiver with UTOPIA Interface]
分类和应用: 异步传输模式ATM
文件页数/大小: 161 页 / 1722 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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2.0 Functional Description  
CN8223  
2.6 ATM Cell Processing  
ATM Transmitter/Receiver with UTOPIA Interface  
Table 2-18. Overhead Field Locations  
Overhead Field  
Source  
Cell Header  
Header Register TX_HDR or FIFO input  
HEC Generation Circuit or FIFO input  
FIFO Input  
Header Error Control  
Segment Type  
Sequence Count  
Length Field  
FIFO Input  
FIFO Input  
Payload CRC  
Payload CRC Generation Circuit or FIFO Input  
Disable HEC [bit 9] and Disable Payload CRC [bit 10] in the CELL_GEN_x  
registers [0x040x07], disable the field generation and allow the existing field to  
pass. Error HEC [bit 11] and Error Payload CRC [bit 12] force a single error  
occurrence in the generated field. The Error functions are cleared after the error  
is generated. This allows the microprocessor to easily generate a specific number  
of errors. The error pattern programmed in the TXFEAC_ERRPAT register  
[0x03] is used with the Error HEC control to generate a specific number of HEC  
errors for checking receiver error correction/detection circuitry.  
The Error Payload CRC bit inserts 4-bit errors into the payload CRC field.  
The Inhibit Single Cell Generation [bit 13] field in CELL_GEN_x, inhibits cell  
transmission from the port for a single cell interval. A single idle cell (with header  
contents as defined in the Transmit Idle Header Register [0x0A0x0B] and  
payload set to all 0s) is transmitted in place of a data cell from this port at the next  
cell interval if the priority control tries to obtain a cell from this port. This bit is  
cleared by the cell generation circuitry after the idle cell has been transmitted or if  
a cell from another port is selected by the priority control. The microprocessor  
can poll this bit to determine when the idle cell insertion has been completed.  
Idle cells are automatically generated when no transmit port is active. The  
header for idle cells is obtained from the TX_IDLE_xx registers, and the HEC is  
automatically calculated. The payload for idle cells is obtained from the  
IDLE_PAY register [0x2A]. This data octet is inserted in all octet positions of the  
idle cell payload. The CRC-10 can be inserted if required by setting Disable  
Payload CRC of CELL_GEN_x to zero.  
2.6.1.2 Cell Generation  
Status and Status  
Interrupts for Transmit  
A per-port count of cells transmitted is maintained in the CELL_SENT_CNTx  
counters [0x4E0x51] for each port. These counters can be programmed to cause  
an interrupt in the CELL_STATUS register [0x3B] by setting enable bits in the  
EN_CELL_INT register 0x30]. The interrupt clears when CELL_STATUS is  
read. If the counter interrupt is not enabled, the counter stops at its maximum  
value of 65,535. If the interrupt is enabled, the counter interrupts on roll over”  
and continues counting. The counter clears when it is read.  
2-28  
Conexant  
100046C