CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.2 Line Framers
2.2 Line Framers
This section describes the operation and control of the internal framers for DS3,
E3 (both G.751 and G.832), E4 (G.832), STS-1, and STS-3c/STM-1 formatted
serial streams. The transmit and receive serial interfaces can operate at up to
155 MHz. Detailed timing information for the line interface is given in
Chapter 4.0.
The framer receive circuitry recovers the frame location from the serial stream
and provides cell octets to the HEC/PLCP cell alignment block. All alarm and
error conditions are monitored and reported in status registers and event counters.
The framer transmit circuitry receives cell octets from the HEC/PLCP cell
alignment block and adds line framing overhead information. All alarm and error
conditions can be generated from control registers.
External interfaces to this block and the interface to the rest of the CN8223 are
illustrated in Table 1-2. The CN8223 line mode is set for both transmit and
receive in the CONFIG_1 register [0x00]. Table 2-1 lists the valid line modes set
by CONFIG_1.
Table 2-1. Valid CONFIG_1 Line Mode Settings, Bits 7–0
Disable
B3ZS/
HDB3
Enable
Parallel
Interface
Enable
HEC
Align
PHY
Type of Line Input Signal
Type
Unframed
Input
External
Framer
DS1
0
0
1
1
2
2
2
3
3
3
0
1
0
1
0
0
1
0
0
1
0
1
1
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0 or 1
DS1 (externally gapped 192 bits/frame)
E1
0
0
0
0 or 1
E1 (externally gapped TS0 and TS16)
DS3, internal framer
0
0
0 or 1
0 or 1
DS3, external framer
0
0 or 1
DS3, external framer (gapped 84/85 bits)
E3, internal G.751 format
E3, external G.751 format
0
0 or 1
0
0
0
0
0
E3, external G.751 format (gapped first 16
bits)
0
E3, internal G.832 format
4
5
6
7
0
x
x
x
x
x
0 or 1
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
E4, internal G.832 format
1
0 or 1
1
STS-1, internal framer
STS-3c/STM-1, internal framer
Parallel or TAXI interface, 53 octet cells
NOTE(S): x = Don’t Care.
0
100046C
Conexant
2-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
