CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.4 Transmit Control Registers
0x08—TX_RATE_23 (Transmit Rate Control Register)
The TX_RATE_23 register is located at address 0x08. Each 8-bit field controls the maximum transmission rate
for ports 3 or 2. These fields are used to control the percentage of the total line rate allocated to each of the four
FIFO transmit ports. Setting these fields to 0 stops transmission on the port. Setting to 0xFF allows the
maximum available rate. Transmit rate control is described in Section 2.7.3.
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Rate Value-Port 3
Rate Value-Port 2
Maximum rate: 0x00 to 0xFF
Maximum rate: 0x00 to 0xFF
0x09—TX_RATE_01 (Transmit Rate Control Register)
The TX_RATE_01 register is located at address 0x09. Each 8-bit field controls the maximum transmission rate
for ports 1 or 0. These fields are used to control the percentage of the total line rate allocated to each of the four
FIFO transmit ports. Setting these fields to 0 stops transmission on the port. Setting to 0xFF allows the
maximum available rate. Transmit rate control is described in Section 2.7.3.
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Rate Value-Port 1
Rate Value-Port 0
Maximum rate: 0x00 to 0xFF
Maximum rate: 0x00 to 0xFF
0x0A—TX_IDLE_12 (Transmit Idle Header Register)
The TX_IDLE_12 register is located at address 0x0A. This register sets the ATM idle cell header octets 1 and 2.
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Header Octet 1
Header Octet 2
Normally written to 00.
Normally written to 00.
0x0B—TX_IDLE_34 (Transmit Idle Header Register)
The TX_IDLE_34 register is located at address 0x0B. This register sets the ATM idle cell header octets 3 and 4.
Field
Size
Bit
Name
Description
15–8
7–0
8
8
Header Octet 3
Header Octet 4
Normally written to 00.
Normally written to 01.
100046C
Conexant
3-17
CONEXANT [ CONEXANT SYSTEMS, INC ]
