3.0 Registers
CN8223
3.4 Transmit Control Registers
ATM Transmitter/Receiver with UTOPIA Interface
0x04–0x07—CELL_GEN_x (Cell Generation Control Registers)
The CELL_GEN_x registers are located at addresses 0x04–0x07. Each of the four FIFO ports has its own ATM
Cell Generation Control Register, so x is 0, 1, 2 or 3. Cell generation is described in detail in Section 2.6. A
description of CELL_GEN_x Control Register addresses is provided in Table 3-7.
Table 3-7. CELL_GEN_x Control Register Addresses
Address
0x04
Register Name
CELL_GEN_0
Description
Cell Generation Control—Port 0 + UTOPIA
Cell Generation Control—Port 1
Cell Generation Control—Port 2
Cell Generation Control—Port 3
0x05
0x06
0x07
CELL_GEN_1
CELL_GEN_2
CELL_GEN_3
Field
Size
Bit
Name
Description
15, 14
13
2
Reserved
Set to 0.
1
1
1
1
1
Inhibit Single Cell
Generation
Inhibits cell transmission from the port for a single cell period and inserts an idle
cell in its place.
12
11
10
9
Error Payload CRC
Forces an error in the payload CRC-10 field. A single error is generated; then this
bit is cleared.
Error HEC
Forces an error in the ATM header HEC field. A single error is generated; then this
bit is cleared.
Disable Payload
CRC
Disables payload CRC-10 field generation and allows the existing field from the
FIFO input to pass.
Disable HEC
Disables the ATM header HEC field (octet 5) generation and allows the existing field
from the FIFO input to pass. The error mask in the TXFEAC_ERRPAT register
controls which bits are errored in the HEC field by XOR’ing this mask with the
calculated HEC, allowing the microprocessor to generate a specific number of
errors.
8
7
1
1
Insert CLP
Insert PT
Performs the same insertion function as Insert GFC (bit 4) for the CLP bit.
Performs the same insertion function as Insert GFC (bit 4) for the 3-bit payload
type field.
6
5
4
1
1
1
Insert VCI
Insert VPI
Insert GFC
Performs the same insertion function as Insert GFC (bit 4) for the 16-bit VCI field.
Performs the same function as the Insert GFC (bit 4) for the 8-bit VPI field.
Allows the 4-bit GFC field obtained from the FIFO interface to be overwritten with
the value programmed in the corresponding TX_HDR registers [0x0C–0x13]. This
bit is only valid in 52-, 53-, and 57-octet modes. In 48-octet mode, the GFC field is
always taken from the TX_HDR register.
3, 2
1, 0
2
2
Port Priority
Allows the cell generator to assign four priority levels to the transmit source.
Cell Generation
Mode
Selects the mode of operation for the generation circuit.
0 0 48 octet
0 1 52 octet
1 0 53 octet
1 1 57 octet
3-16
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
