4-Level FSK Modem Data Pump
Page 46 of 50
MX929B PRELIMINARY INFORMATION
6.1.3.1 Operating Characteristics Notes:
1. Not including any current drawn from the modem pins by external circuitry other than the Xtal oscillator.
2. Small signal impedance.
3. Measured after the external RC filter (R4/C5) for a "+3 +3 -3 -3...." symbol sequence. (Tx output level is
proportional to V ).
DD
4. Measured at the TXOUT pin with the modem in the Tx idle mode.
5. For optimum performance, measured at RXAMPOUT pin, for a "...+3 +3 -3 -3..." symbol sequence,
TXIMP = 0 or 1. The optimum level and DC offset values are proportional to V
6. Timing for an external input to the XTAL/Clock pin.
7. WR , RD , CS , A0 and A1 pins.
.
DD
8. D0 - D7 pins.
9. IRQ pin.
6.1.4 Timing
Notes
Min.
Typ.
Max.
Units
PC Parallel Interface Timings (ref. Figure 28)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
0
ns
Address valid to CS low time
Address hold time
ACSL
0
0
ns
ns
AH
CS hold time
CS high time
CSH
1
6.0
0
clock cycles
CSHI
CSRWL
DHR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS to WR or RD low time
Read data hold time
Write data hold time
0
0
90.0
0
DHW
DSW
RHCSL
RACL
RARL
RL
Write data setup time
RD high to CS low time (write)
Read access time from CS low
Read access time from RD low
RD low time
RD high to D0-D7 3-state time
WR high to CSlow time (read)
WR low time
2
2
175
145
200
50
RX
0
WHCSL
t
200
ns
WL
6.1.4.1 Timing Notes:
1. Xtal/Clock cycles at the XTAL/CLOCK pin.
2. With 30pF max to V on D0 - D7 pins.
SS
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