GMSK Modem Data Pump
Page 29 of 37
MX909A PRELIMINARY INFORMATION
AQLEV Sequence
AQBC Sequence
SFH or SFS is set up to 28 bits after AQLEV;
Frame Sync is being searched for:
1 bit of clamp.
Lossy Peak detect until Frame Sync is
detected.
SFH or SFS is set up to 14 bits after AQBC;
Frame Sync is being searched for:
'Wide' setting until Frame Sync detected.
30 bits of 'Medium' setting.
Residual setting.
Residual setting.
SFH or SFS is not set; Frame Sync is not
being searched for:
1 bit of clamp.
30 bits of Lossy Peak Detect.
Residual setting.
SFH or SFS is not set; Frame Sync is not
being searched for:
16 bits of 'Wide' setting.
30 bits of 'Medium' setting.
Residual setting.
Noise
Bit Sync
Frame Sync
Rest of Frame
Rx Signal from
FM discriminator
to Modem
2-Bit delay (min.)
Set AQBC and AQLEV bits
to start Acquisition sequences
Level Measurement and clock
extraction circuits
Increasing accuracy and lengthening response times
RESET
Figure 16: Bit Clock and Level Acquisition Example
¤2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480134.005
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