GMSK Modem Data Pump
Page 26 of 37
MX909A PRELIMINARY INFORMATION
5.2 Receive Frame Example
If the device is required to decode a Mobitex¥ Frame the following control signals should be issued to the
modem, assuming the device is initially not in powersave, PLLBW, LEVRES, SCREN are set as
required, TX/RX bit is set to '0', the Frame Sync bytes have not been set and the carrier has been detected,
or a Frame Head is expected:
1.
2.
2 Frame Sync bytes are loaded.
2 bits after the carrier has been detected, an LFSB task is loaded, along with setting the AQLEV and
AQBC bits, to initiate the level acquisition and bit clock extraction sequences.
3.
4.
Device interrupts host µC with IRQ when 2nd byte is read from Data Buffer.
Status Register is read, 12 bits later task is set to SFH to search for a Mobitex¥ Frame Head.
5.
Device will interrupt host µC with IRQ when valid Frame Sync is detected and header bytes
decoded.
6.
Host µC reads Status Register, checks MO/BA and CRCFEC bit and reads out 2 Frame Head control
bytes.
7.
8.
Host µC sets the task to RDB to receive a Mobitex¥ Data Block.
Device will interrupt host µC with IRQ when the Data Block has been received and the CRC has
been calculated.
9.
Host µC reads Status Register, checks CRC validity and reads 18 Data Block bytes. The Data
Quality Register can also be read to obtain the received S/N level.
10.
Host µC sets task if more information is expected:
GOTO '4'
GOTO '7'
if last Data Block and another Frame Head are expected.
if another Mobitex¥ Data Block is expected.
If the last Data Block has been decoded and no further information is expected, then the task bits do not need
to be set, as the device will automatically select the idle state.
A top level flowchart of the receive process is shown in Figure 15.
¤2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480134.005
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