GMSK Modem Data Pump
Page 21 of 37
MX909A PRELIMINARY INFORMATION
4.4.5.5 Status Register B3: CRCFEC - CRC or FEC Error
In receive mode this bit will be updated at the end of a Mobitex¥ Data Block task, after checking the CRC,
and at the end of receiving Frame Head control bytes, after checking the FEC. A '0' indicates that the CRC
was received correctly or the FEC did not find uncorrectable errors, a '1' indicates that errors are present.
The bit is cleared to '0' by a RESET task or by changing the PSAVE or TX/RX bits of the Mode Register.
In transmit mode this bit will be '0'.
4.4.5.6 Status Register B2: DQRDY - Data Quality Reading Ready
In receive mode, this bit is set to '1' whenever a Data Quality reading has been completed. See section 4.4.6.
The bit is cleared to '0' by a read of the Data Quality Register.
Immediately after a RESET task, or a change in the PSAVE or TX/RX bits to '0', the DQRDY bit may be set
and generate an interrupt. The value in the Data Quality Register will not be valid in this case.
4.4.5.7 Status Register B1: MO/BA - Mobile or Base Bit Sync Received
In receive mode this bit is updated at the end of the SFS and SFH tasks. This bit is set to '1' whenever the 3
bits immediately preceding a detected Frame sync are '011' (received left to right), with up to any one bit in
error. The bit is set to '0' if the bit pattern is '100', again with up to any one bit in error. Thus, if this bit is set
to '1' then the received message is likely to have originated from a Mobile and if it is set to '0' from a Base
Station. See section 4.3.
In transmit mode this bit is a logic '0'.
4.4.5.8 Status Register B0
This bit will always be set to '0'.
4.4.6 Data Quality Register
This is intended to indicate the quality of the receive signal during a Mobitex¥ Data Block or 30 single bytes.
In receive mode, the modem measures the 'quality' of the received signal by comparing the actual received
zero crossing time against an internally generated time. This value is averaged over 240 bits and at the end
of the measurement the Data Quality Register and the DQRDY bit in the Status Register is updated.
Note: An interrupt will only occur at this time if the DQEN bit = '1'.
To provide Synchronization with Data Blocks, and to ensure the Data Quality Register is updated in
preparation to be read when the RDB task finishes, the measurement process is reset at the end of tasks
SFH, SFS, RDB and R3H.
In transmit mode all bits of the Data Quality Register will be '0'.
Figure 12 shows how the value (0-240) read from the Data Quality Register varies with received signal to
noise ratio.
240
220
200
180
160
140
120
100
80
60
40
20
0
3
4
5
6
7
8
9
10
11
12
Received Signal-to-Noise Ratio (dB)
Figure 12: Typical Data Quality Reading (after 240 bits) vs. S/N, (noise in bit rate bandwidth)
¤2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480134.005
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