GMSK Modem Data Pump
Page 17 of 37
MX909A PRELIMINARY INFORMATION
4.4.2.19 Tx/Rx Low Pass Filter Delay
The previous task timing figures are based on the signal at the input to the Tx Low Pass filter (in transmit
mode) or the input to the de-interleave buffer (in receive mode). There is an additional delay of about 2 bit
times in both transmit and receive modes due to the Tx/Rx Low Pass filter, as illustrated in Figure 11.
Figure 11: Low Pass Filter Delay
4.4.3 Control Register
This 8-bit write only register controls the modem's bit rate, the response times of the receive clock extraction
and signal level measurement circuits and the internal analog filters.
Control Register
7 6 5 4 3 2 1 0
CKDIV
HI/LO DARA
LEVRES
PLLBW
4.4.3.1 Control Register B7, B6: CKDIV - Clock Division Ratio and B5: HI/LO - Xtal Range Selection
These bits control a frequency divider driven from the clock signal present at the XTAL pin, which determines
the nominal bit rate. The table below shows how bit rates of 4000/8000/16000 or 4800/9600/19200 bits/sec
may be obtained from common Xtal frequencies:
B5
XTAL / CLOCK Frequency (MHz)
1
8.192
9.8304
4.096
4.9152
2.048
2.4576
(12.288/3)
(6.144/3) (12.288/5)
0
4.096
4.9152
2.048
2.4576
1.024
1.2288
(12.288/3)
(6.144/3)
(12.288/5)
Division Ratio:
XTAL Frequency
B7
B6
Data Rates (bits per second)
Data Rate
0
0
1
1
0
1
0
1
256
512
128
256
16000
8000
4000
19200
9600
4800
8000
4000
9600
4800
16000
8000
4000
19200
9600
4800
1024
2048
512
1024
Note: Device operation is not guaranteed below 4000 or above 19200 bits/sec.
The values used for C3 and C4 should be suitable for the frequency of the crystal X1. As a guide; C3 = C4 =
33pF for X1 < 5MHz, and C3 = C4 = 18pF for X1 > 5MHz.
¤2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480134.005
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