GMSK Modem Data Pump
Page 12 of 37
MX909A PRELIMINARY INFORMATION
4.4.2.2 Command Register B6: AQLEV - Acquire Receive Signal Levels
This bit has no effect in transmit mode.
In receive mode, when a byte with AQLEV bit set to '1' is written to the Command Register and TASK is not
set to RESET, it initiates an automatic sequence designed to measure the amplitude and DC offset of the
received signal as rapidly as possible. This sequence involves setting the measurement circuits to respond
quickly at first, then gradually increasing their response time, thereby improving the measurement accuracy,
until the 'normal' value set by the LEVRES bits of the Control Register is reached.
Setting this bit to '0' (or changing it from '1' to '0') has no effect, however the acquisition sequence will be re-
started every time a byte written to the Command Register has the AQLEV bit set to '1'.
The AQLEV bit will normally be set up to 12 bits before an SFS (Search for Frame Sync) or SFH (Search for
Frame Head) task is initiated, however it may also be used independently to re-establish signal levels quickly
after a long fade. Alternatively, an SFS or SFH task may be written to the Command Register with the
AQLEV bit at '0' if it is known that there is no need to re-establish the received signal levels. Further
information of the level measurement acquisition sequence is provided in section 5.3.
The error rate is highest immediately after an AQBC and AQLEV sequence is triggered and rapidly reduces to
its static value soon after. These erroneous bits could incorrectly trigger the frame sync detection circuits. It
is suggested that an SFH or SFS task be set 12 bits after setting either of the AQLEV or AQBC sequences.
4.4.2.3 Command Register B5, B4, B3
These bits should be set to '0'.
4.4.2.4 Command Register B2, B1, B0: TASK - Task
Operations such as transmitting a data block are treated by the modem as 'tasks' and are initiated when the
µC writes a byte to the Command Register with the TASK bits set to anything other than the 'NULL' code.
The µC should not write a task (other than NULL or RESET) to the Command Register or write to or read
from the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is '0'.
Different tasks apply in receive and transmit modes.
When the modem is in transmit mode, all tasks other than NULL, RESET and TSO instruct the modem to
transmit data from the Data Buffer, formatting it as required. For these tasks the µC should wait until the
BFREE (Buffer Free) bit of the Status Register is '1', before writing the data to the Data Buffer, then it should
write the desired task to the Command Register. If more than 1 byte needs to be written to the Data Buffer,
byte number 0 of the block should be written first.
Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE (Buffer Free) bit of the Status Register to '0'.
Take the data from the Data Buffer as quickly as it can - transferring it to the Interleave Buffer for
eventual transmission. This operation will start immediately if the modem is 'idle' (i.e. not transmitting
data from a previous task), otherwise it will be delayed until there is sufficient room in the Interleave
Buffer.
Once all of the data has been transferred from the Data Buffer the modem will set the BFREE and
IRQ bits of the Status Register to '1', (causing the chip IRQ output to go low if the IRQEN bit of the
Mode Register has been set to '1') to tell the µC that it may write new data and the next task to the
modem.
In this way the µC can write a task and the associated data to the modem while the modem is still transmitting
the data from the previous task. See Figure 7.
When the modem is in receive mode, the µC should wait until the BFREE bit of the Status Register is '1', then
write the desired task to the Command Register.
Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE bit of the Status Register to '0'.
Wait until enough received bits are in the De-interleave Buffer.
Decode them as needed, and transfer any resulting data to the Data Buffer
Then the modem will set the BFREE and IRQ bits of the Status Register to '1', (causing the IRQ
output to go low if the IRQEN bit of the Mode Register has been set to '1') to tell the µC that it may
read from the Data Buffer and write the next task to the modem. If more than 1 byte is contained in
the Data Buffer, byte number '0' of the data will be read first.
¤2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480134.005
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