Digitally Controlled Analog I/O Processor
18
MX839 PRELIMINARY INFORMATION
6.1.4 Timing
For the following conditions unless otherwise specified:
DV = 3.3V to 5.0V, T
= 25°C
AMB
DD
Parameter
Min.
Typ.
Max.
Units
t
"CS-Enable to Clock-High"
2.0
µs
CSE
t
Last "Clock-High to CS-High"
"CS-High to Reply Output 3-state"
4.0
µs
µs
µs
µs
µs
CSH
t
2.0
HIZ
t
"CS-High" Time between transactions
"Inter-Byte" Time
2.0
4.0
2.0
CSOFF
t
NXT
t
"Clock-Cycle" time
CK
tCSOFF
CS
tCSE
tNXT
tCSH
tNXT
SERIAL CLOCK
COMMAND DATA
tCK
1
0
7
1
5 4 3 2
6
0
0
7
MSB
6
5 4 3 2
1 0
LSB
7
7
6
5 4 3 2
FIRST DATA BYTE
LAST DATA BYTE
ADDRESS/COMMAND
BYTE
tHIZ
REPLY DATA
1
0
7
5
6
4
1
3
2
5
4
3
2
6
MSB
LSB
LAST REPLY DATA BYTE
FIRST REPLY DATA BYTE
Logic level is not important
Figure 5: 'C-BUS' Timing
Timing Notes:
1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral MSB (Bit 7) first,
LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0) last.
2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge.
3. Loaded commands are acted upon at the end of each command.
4. To allow for differing µC serial interface formats 'C-BUS' compatible ICs are able to work with either polarity
SERIAL CLOCK pulses.
© 1998 MXxCOM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CMLMICRO [ CML MICROCIRCUITS ]
