1200/2400bps MSK Modem for Trunked Radio Systems
9
MX429A
Bit
Description
Function
(i). by a read of the Status Register
(ii). by Tx Enable going Low.
Bit 4
D4
Tx Idle
D4: causes an interrupt when set, to indicate that all loaded data and one 'hang' bit
have been transmitted.
Set: one bit period after the last byte is transmitted. This last byte could be either
“checksum” or “ loaded data” depending upon the Tx Parity Enable state (Control
Register D1).
Bit Cleared:
(i). by a write to the Tx Data Buffer
(ii). by Tx Enable going Low.
Interrupt Cleared:
(i). by a read of the Status Register
(ii). by Tx Enable going Low.
Bit 5
D5
Timer Interrupt
D4: causes an interrupt when set, to indicate that all loaded data and one 'hang' bit
have been transmitted.
Set: one bit period after the last byte is transmitted. This last byte could be either
“checksum” or “ loaded data” depending upon the Tx Parity Enable state (Control
Register D1).
Bit Cleared:
(i). by a write to the Tx Data Buffer
(ii). by Tx Enable going Low
Interrupt Cleared:
(i). by a read of the Status Register
(ii). by Tx Enable going Low.
Bit 6
D6
Rx SYNC
Detect *
D6: when set, causes an interrupt to indicate that a 16-bit 'SYNC' word
(1100010011010111) has been detected in the received bit stream.
Set: on receipt of the 16th bit of a 'SYNC' word.
Bit and Interrupt Cleared:
(i). by a read of the Status Register
(ii). by Rx Enable going Low.
Bit 7
D7
Rx SYNT
Detect *
D7: when set, causes an interrupt to indicate that a 16-bit 'SYNT' word
(0011101100101000 ) has been detected in the received bit stream.
Set: on receipt of the 16th bit of a 'SYNT' word.
Bit and Interrupt Cleared:
(i). by a read of the Status Register
(ii). by Rx Enable going Low.
* SYNC and SYNT Detection is disabled while the checksum checker is running.
Table 6: Status Register
4.1.6 Rx Data Buffer (A1 = 1, A0 = 0, R/W = 1, Read Only)
These 8 bits are the last byte of data received with bit 7 being received first. Note the relative positions of the
MSB and LSB presented in this bit stream, the position may be different to the convention used in other
µProcessor peripherals.
D0
D1
D2
D3
D4
D5
D6
D7
LSB
MSB
4.1.7 Tx Data Buffer (A1 = 1, A0 = 0, R/W = 0, Write Only)
These 8 bits loaded to the Tx Data Buffer are the next byte of data that will be transmitted, with bit 7 being
transmitted first. Note the relative positions of the MSB and LSB presented in this bit stream, the position may
be different to the convention used in other µProcessor peripherals. If the Tx Parity Enable bit (Control
Register D1 ) is set, a 2–byte checksum will be inserted and transmitted by the modem after every 6
transmitted “message” bytes.
D0
D1
D2
D3
D4
D5
D6
D7
LSB
MSB
© 1998 MX-COM Inc.
www.mxcom.com Tel: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480128.007
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