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MX429AJ 参数 Datasheet PDF下载

MX429AJ图片预览
型号: MX429AJ
PDF下载: 下载PDF文件 查看货源
内容描述: [Modem, 2.4kbps Data, CMOS, CDIP24, CERAMIC, DIP-24]
分类和应用: 调制解调器无线
文件页数/大小: 20 页 / 464 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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1200/2400bps MSK Modem for Trunked Radio Systems  
7
MX429A  
4.1.3 Non MPT Application – Full-Duplex  
The functions described in this section, to allow the MX429A modem to operate as a general purpose device,  
are obtained using the commands and indications detailed in the “Register Instructions” pages.  
Tx: When enabled the device transmits a “101010......10” preamble until data for transmission is loaded by  
the host microprocessor. Transmits 6 bytes of the loaded data followed by a 2-byte checksum based on  
that data. As long as Tx data is loaded the transmitter will transmit, the 2-byte checksum being produced  
after every 6 bytes (8 byte packages). Automatic checksum generation can be inhibited by a software  
command to allow transmission of continuous data streams.  
Rx: When enabled requires the 16-bit SYNC or SYNT word (see notes) before outputting data bytes. The  
modem receiver will then output continuous bytes of data, after every 6 bytes received a 2-byte  
checksum word will be output and can be ignored or used for error checking.  
4.1.4 Control Register (A1 = 1, A0 = 1, R/W = 0, Write Only)  
The Control Register, when selected, directs the modem’s operation as described in Table 4  
Bit  
Description  
Function  
Bit 0  
D0  
TX Enable  
Set: D0 enables the transmitter for operation. A '0 – 1' transition causes bit  
synchronization and the start of 1010.........10 preamble pattern transmission. At least  
one byte of preamble will be transmitted. If data is loaded into the Tx Data Buffer before  
one byte has been sent then that data will follow, otherwise whole bytes of preamble will  
continue until data is loaded.  
Clear: The Transmitter Output pin is set to a high impedance and no transmitter  
interrupts are produced.  
Bit 1  
D1  
Tx Parity  
Enable  
Set: D1 indicates to the transmitter that 2–byte checksums are to be generated by the  
modem. A '0 – 1' transition starts checksum generation on the next six bytes loaded  
from the Tx Data Buffer into the Tx Data Register. Checksum generation continues for  
every 6 bytes loaded until this bit is cleared. The transmitter will send the generated  
checksum (2 bytes) after the last of each 6 bytes have been sent. If an underrun (no  
more data loaded) condition occurs before 6 bytes have been loaded checksum  
generation will abort, the transmission will cease after one 'hang' bit has been sent and  
Bit 4 in the Status Register (Tx Idle) will be set. No checksum will be transmitted.  
Clear: No checksum generation is carried out and the host may supply the checksum  
bytes. The output is then “as written”.  
Bit 2  
D2  
Rx Enable  
Set: D2 enables the receiver for operation. No data is produced (i.e. No Rx Data  
Ready interrupts) until a 'SYNC' or 'SYNT' word is found in the received bit stream.  
Clear: The receiver is disabled and all interrupts caused by the receiver are inhibited.  
Bit 3  
D3  
Rx Message  
Format  
Set: D3 is sampled after a checksum has been received and allows the host to control  
the way the receiver handles the following data bits. If 'set' the receiver will assume that  
the next 6 bytes are data and will start error checking accordingly.  
Clear: The receiver will stop data transfer to the host after the 2 checksum bytes until  
another 'SYNC' or 'SYNT' frame word is received.  
Bit 4  
D4  
Timer LSB  
Timer  
Bit 5  
D5  
Reference Table 5  
Bit 6  
D6  
Timer  
Bit 7  
D7  
Timer MSB  
If a new timer value is written to these inputs within 1 byte period of the last timer  
interrupt then the next timer period will be correct without first having to reset the timer,  
otherwise the timer must be reset to zero and then set to the new time.  
Tx Enable  
If using the internal Tx preamble generation facility, e.g. with the internal timer setting  
the preamble length, the device may occasionally produce a Tx Ready interrupt  
immediately after a Tx Enable command. User software should handle this occurrence  
by either:  
a. Detecting that the timer interrupt status bit is not set and that it is not appropriate to  
load Tx data at this time.  
b. Not using the timer. i.e. immediately after Tx Enable, reading the Status Register and  
loading a byte of preamble. This resets any interrupt. The length of preamble  
transmitted is now controlled by the number of bytes loaded.  
© 1998 MX-COM Inc.  
www.mxcom.com Tel: 800 638-5577 336 744-5050 Fax: 336 744-5054  
Doc. # 20480128.007  
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA  
All trademarks and service marks are held by their respective companies.  
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