FRS Signalling Processor
CMX882
1.5.5.3
Frame Head
The Frame Head forms an important part of a frame as it allows the receiver to detect and lock on to
MSK signals, provides basic addressing to screen out unwanted messages and indicates the format,
coding and length of any following data.
The 4 Control Field bytes have Forward Error Correction (FEC) applied to them in the transmitter, this
adds 4 bits to every byte and the receiver can correct errors in the received bytes. The 4 received bytes
are then checked for a correct CRC so corrupted Frame Heads can be rejected. If checksum A indicates
that the Control Field bytes are correct, the Address (byte 1) is compared with that stored in the Device
Address bits of register $C2. If a match occurs, or if the received address is '40' then an interrupt is
raised indicating a valid Frame Head has been received. The Frame Head is 80 bits long (16 + 16 +
{4x12}).
1.5.5.4
Data Block Coding
The Data Block follows the Frame Head and can be coded with different levels of error correction and
detection. The Data Block format is controlled by Frame Head byte 2, see also section 1.6.11.
Messages can take the following formats:
Type:
0
Description:
Raw data, the CMX882 will transmit 16 bits at a time. In receive the device will search for the
programmed 16 bit frame sync pattern and then output all following data 16 bits at a time, the
host will have to perform all other data formatting. The data scrambler does not operate in this
mode. This mode can be useful when interfacing to a system using a different format to those
available in the CMX882.
1
2
Frame Head only, no User Data will be added. This format can be useful for indicating channel
or user status by using byte 3 and the User Bit of the Frame Head.
Frame head followed by raw data. User data is appended to the Frame Head in 2 byte units
with no formatting or CRC added by the CMX882. No size information is set in the Frame Head
and User Data may contain any even number of bytes per Frame.
3
4
Frame Head followed by FEC coded data only. Each byte of the User Data has 4 bits of FEC
coding added. No size information is set in the Frame Head and User Data may contain any
even number of bytes per Frame. No CRC is added to the data.
Frame Head followed by FEC coded data with an automatic CRC at the end of the User Data.
The number of User Data bytes in the Frame must be set in Frame Head byte 3. The CRC is
automatically checked in the receiver and the result indicated to the host. Up to 255 bytes of
User Data can be sent in each Frame using this format.
5
As per ‘4’ with the addition of all Data Block bytes being interleaved. This spreads the
transmitted information over time and helps reduce the effect of errors caused by fading.
Interleaving is performed on blocks of 4 bytes, the CMX882 automatically adds and strips out
pad bytes to ensure multiples of 4 bytes are sent over the radio channel.
Notes:
•
Message types 1, 2 and 3 have no size information requirement and do not reserve Frame Head
byte 3. This byte may be freely used by the host to convey information. In message types 4 and
5 this byte must be set to the number of User Bytes in the message attached to that Frame Head
(≤255) to allow the receiver to correctly decode and calculate the CRC.
•
•
Type 0 data transfers do not use frame heads. In Tx the host must transfer the bit and frame
sync data before sending the message data. In Rx the host must decode all data after the frame
sync.
When using type 0 (raw data) messages it is strongly recommended that the default Frame Sync
pattern is not used. This is to reduce the loading on receivers using the formatted data types
which would otherwise try to decode the 6 bytes following a type 0 frame sync as a Frame Head.
2004 CML Microsystems Plc
30
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
