FRS Signalling Processor
CMX882
The table below shows the combinations of frequencies and number of cycles to represent each bit of
data, for both baud rates.
Table 8 Data Frequencies for each Baud Rate
Baud Rate
1200 baud
Data
Frequency
1200Hz
1800Hz
1200Hz
2400Hz
Number of Cycles
1
0
1
0
one
one and a half
half
2400 baud
one
Note: FFSK may be transmitted in conjunction with a CTCSS or DCS sub-audio component.
1.5.4.6 Transmitting XTCSS Signalling
XTCSS signals can be transmitted by loading the 4 tone pattern and CTCSS tone into the C-BUS
registers and enabling XTCSS. The device will transmit the 4 tones in sequence, raise an interrupt when
this is complete and then automatically generate the CTCSS tone (if enabled). At the end of the
message the CTCSS tone can be disabled by setting the CTCSS enable bit to '0'. The XTCSS 4 tone
sequence must be transmitted on its own, so if a voice or a data signal is being transmitted, this must be
disabled during the XTCSS 4 tone transmission. See section 1.5.6 for more information.
1.5.5
FFSK/MSK Data Packeting
The CMX882 has extensive data packeting features that can be controlled by the Modem Control register
($C7). The CMX882 can packet data in a variety of formats so the user can have the optimum data
throughput for various signal to noise ratios. Data is transferred in packets or frames, each frame is
made up of a Frame Head followed by any associated User Data. The Frame Head is composed of a 16
bit Bit Sync and 16 bit Frame Sync pattern immediately followed by 4 bytes of data. The 4 bytes of data
start with an 8 bit address followed by 1 byte carrying information about the format of the following Data
Block, a further byte indicates the size of the packet and the last byte is a checksum to detect if any of
the 4 Frame Head bytes has been corrupted.
1.5.5.1
Tx Hang bit
When transmitting FFSK/MSK data the user should ensure that the data is terminated with a hang bit. To
do this, the host must set the 'Last Data' bit in the Modem Control Register ($C7) after the last data word
has been loaded into the Tx Data register, as described in section 1.6.11. This will append a hang bit
onto the end of the current word and will stop modulating after the hang bit has been transmitted. It will
also generate (if enabled) an interrupt when the hang bit has left the modulator.
1.5.5.2
Frame format
←---------------------------------Frame Head---------------------------------→
←--------Data Block--------→
←---Sync Field---
←------------------Control Field------------------→
→
Bit
Frame
Sync
Address
byte
Format
byte
Size^ or
User byte
Byte 3
Check-
sum A
Byte 4
Data
Check-
sum B*
Sync
16 bits
bytes
16 bits
Byte 1
Byte 2
* Checksum B not applied to all Data Block types
^ Byte 3 is only reserved on sized data blocks.
The Data Block is made up from the User Data. This consists of a variable number of data bytes
optionally encoded to ensure secure delivery over a radio channel to the receiver. Checksum B is only
applied at the end of sized Data Blocks, the receiver can then detect if any of the User Data has been
corrupted. Checksum B is composed of 16 bits for messages ≤16 bytes and 32 bits for longer messages.
2004 CML Microsystems Plc
29
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
