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FX929BD5 参数 Datasheet PDF下载

FX929BD5图片预览
型号: FX929BD5
PDF下载: 下载PDF文件 查看货源
内容描述: [Modem-Support Circuit, CMOS, PDSO24,]
分类和应用: 电信光电二极管电信集成电路
文件页数/大小: 47 页 / 1631 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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4-Level FSK Modem Data Pump  
FX929B  
The 'Header' block is self-contained in that it includes its own checksum (CRC1), and would normally carry  
information such as the address of the calling and called parties, the number of following blocks in the frame (if  
any) and miscellaneous control information.  
The 'Intermediate' block(s) contain only data, the checksum at the end of the 'Last' block (CRC2) also checks  
the data in any preceding 'Intermediate' blocks.  
Proprietary systems which do not use the RD-LAP format may use the block structures provided by the  
FX929B to build alternative frame formats more suited to the particular application. Some examples are  
illustrated in Figure 7a below.  
Figure 7a Some Alternative Frame Structures  
The FX929B performs all of the block formatting and de-formatting, the binary data transferred between the  
modem and its mC being that enclosed by the thick dashed rectangles near the top of Figure 7.  
1.5.5 The Programmer's View  
The modem appears to the programmer as 4 write only 8-bit registers shadowed by 3 read only registers,  
individual registers being selected by the A0 and A1 chip inputs:  
A1  
0
A0  
0
Write to Modem  
Data Buffer  
Read from Modem  
Data Buffer  
0
1
1
1
0
1
Command Register  
Control Register  
Mode Register  
Status Register  
Data Quality Register  
not used  
Note that there is a minimum allowable time between accesses of the modem's registers, see Section 1.7.1 for  
details.  
1.5.5.1 Data Block Buffer  
This is a 12-byte read/write buffer which is used to transfer data (as opposed to command, status, mode, data  
quality or control information) between the modem and the host µC.  
It appears to the µC as a single 8-bit register; the modem ensuring that sequential µC reads or writes to the  
buffer are routed to the correct locations within the buffer.  
The µC should only access this buffer when the Status Register BFREE (Buffer Free) bit is '1'.  
The buffer should only be written to while in Tx mode and read from while in Rx mode. Note that in receive  
mode the modem will function correctly even if the received data is not read from the Data Buffer by the mC.  
ã 1997 Consumer Microcircuits Limited  
13  
D/929B/1