FX909A 参数 Datasheet PDF下载

Wireless Modem Data Pump

FX909A

1.5

General Description

This product has been designed to be compliant with the appropriate sections of the "Mobitex

Interface Specification".

1.5.1

1.5.1.1

Description of Blocks

Data Bus Buffers

8 bidirectional 3-state logic level buffers between the modem's internal registers and the host µC's

data bus lines.

Address and R/W Decode

This block controls the transfer of data bytes between the µC and the modem's internal registers,

according to the state of the Write and Read Enable inputs (WRN and RDN), the Chip Select input

(CSN) and the Register Address inputs A0 and A1.

The Data Bus Buffers, Address and R/W Decode blocks provide a byte-wide parallel µC interface,

which can be memory-mapped, as shown in Figure 3.

1.5.1.2

Figure 3 Typical Modem µC Connections

1.5.1.3

Status and Data Quality Registers

8-bit registers which the µC can read to determine the status of the modem and the received data

quality.

Command, Mode and Control Registers

The values written by the µC to these 8-bit registers control the operation of the modem.

Data Buffer

An 18-byte buffer used to hold receive or transmit data to or from the µC.

1.5.1.4

1.5.1.5

©

1996 Consumer Microcircuits Limited

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