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FX909A 参数 Datasheet PDF下载

FX909A图片预览
型号: FX909A
PDF下载: 下载PDF文件 查看货源
内容描述: CML半导体产品无线调制解调器数据泵 [CML Semiconductor Products Wireless Modem Data Pump]
分类和应用: 调制解调器半导体无线
文件页数/大小: 47 页 / 951 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Wireless Modem Data Pump  
FX909A  
1.5.4.5 Status Register  
This register may be read by the µC to determine the current state of the modem.  
Status Register B7: IRQ - Interrupt Request  
This bit is set to '1' by:  
The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET  
task or by a change to the Mode Register PSAVE or TXRXN bits.  
or  
The Status Register IBEMPTY bit going from '0' to '1', unless this is caused by a  
RESET task or by changing the Mode Register PSAVE or TXRXN bits.  
or  
or  
The Status Register DQRDY bit going from '0' to '1' (If DQEN = '1' ).  
The Status Register DIBOVF bit going from '0' to '1'.  
The IRQ bit is cleared to '0' immediately after a read of the Status Register.  
If the IRQEN bit of the Mode Register is '1', then the chip IRQN output will be pulled low (to Vss)  
whenever the IRQ bit is '1'.  
Status Register B6: BFREE - Data Buffer Free  
This bit reflects the availability of the Data Buffer and is cleared to '0' whenever a task other than  
NULL, RESET or TSO is written to the Command Register.  
In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to '1') by  
the modem when the modem is ready for the µC to write new data to the Data Buffer and the next  
task to the Command Register.  
In receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to '1') by the  
modem when it has completed a task and any data associated with that task has been placed into  
the Data Buffer. The µC may then read that data and write the next task to the Command Register.  
The BFREE bit is also set to '1', but without setting the IRQ bit, by a RESET task or when the Mode  
Register PSAVE or TXRXN bits are changed.  
Status Register B5: IBEMPTY - Interleave Buffer Empty  
In transmit mode, this bit will be set to '1', also setting the IRQ bit, when less than two bits remain in  
the Interleave Buffer. Any transmit task written to the modem after this bit goes to '1' will be too late to  
avoid a gap in the transmit output signal.  
ã 1996 Consumer Microcircuits Limited  
26  
D/909A/4  
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