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FX909A 参数 Datasheet PDF下载

FX909A图片预览
型号: FX909A
PDF下载: 下载PDF文件 查看货源
内容描述: CML半导体产品无线调制解调器数据泵 [CML Semiconductor Products Wireless Modem Data Pump]
分类和应用: 调制解调器半导体无线
文件页数/大小: 47 页 / 951 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Wireless Modem Data Pump  
FX909A  
Mode Register B6: INVBIT - Invert Bits  
This bit controls inversion of transmitted and received bit voltages. When set to '1' all data is inverted  
in the Tx and Rx data paths so a transmitted '1' is a voltage below V at the TXOP pin and a  
BIAS  
received '0' is a voltage above V  
is set to '1'.  
at the RXIN pin. Data will be inverted immediately after this bit  
BIAS  
Mode Register B5: TXRXN - Tx/Rx Mode  
Setting this bit to '1' puts the modem into Transmit mode, clearing it to '0' puts the modem into  
Receive mode. When changing from Rx to Tx there must be a 2-bit pause before setting a new task  
to allow the filter to stabilise. (See also PSAVE bit).  
Note that changing between receive and transmit modes will cancel any current task  
Mode Register B4: SCREN - Scramble Enable  
The scrambler only takes effect during the transmission or reception of a Mobitex Data Block and  
during a TSO task. Setting this bit to '1' enables scrambling, clearing it to '0' disables scrambling.  
The scrambler is only operative, if enabled by this control bit, during TSO, RDB or TDB, it is held in a  
reset state at all other times.  
This bit should not be changed while the modem is decoding or transmitting a Mobitex Data Block.  
Mode Register B3: PSAVE - Powersave  
When this bit is a '1', the modem will be in a 'powersave' mode in which the internal filters, the Rx bit  
and Clock extraction circuits and the Tx o/p buffer will be disabled, and the TXOP pin will be  
connected to V  
through a high value resistance. The Xtal Clock oscillator and the µC interface  
BIAS  
logic will continue to operate.  
Setting the PSAVE bit to '0' restores power to all of the chip circuitry. Note that the internal filters will  
take about 2 bit times to settle after the PSAVE bit is taken from '1' to '0'.  
Mode Register B2: DQEN - Data Quality IRQ Enable  
In receive mode, setting this bit to '1' causes the IRQ bit of the Status Register to be set to '1'  
whenever a new Data Quality reading is ready. (The DQRDY bit of the Status Register will also be  
set to '1' at the same time.)  
In transmit mode this bit has no effect.  
Mode Register B1, B0  
These bits should be set to '0'.  
ã 1996 Consumer Microcircuits Limited  
25  
D/909A/4  
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