1.3
Signal List (continued)
Package
D4/P3
Signal
Description
Pin No.
10
Name
Type
Power
I/P
V
The negative supply rail (ground).
ss
11
SIGIN
Signal input. The signal to this pin should be ac
coupled. The dc bias of this pin is set internally.
12
VBIAS
O/P
Internally generated bias voltage, held at VDD /2
when the device is not in powersave mode. It
should be decoupled to V by a capacitor
ss
mounted close to the device pins. In powersave
mode this pin is pulled towards VSS
.
13
14
15
AMPNINV
AMPINV
AMPOP
I/P
I/P
The non-inverting input to the on-chip amplifier.
The inverting input to the on-chip amplifier.
O/P
The output of the on-chip amplifier, this is
internally connected to the input of the Level
Detector.
16
VDD
Power
The positive supply rail. Levels and voltages are
dependent upon this supply. This pin should be
decoupled to VSS by a capacitor.
Notes: I/P
=
Input
O/P = Output
ã 1999 Consumer Microcircuits Limited
5
D/663/3
CMLMICRO [ CML MICROCIRCUITS ]
