Codec Timing Information
ENCODER TIMING
TIMING
ENCODER
CLOCK
t
DATA CLOCKED
CH
t
IF
t
CL
t
t
IR
CH
t
CH
Clock '1' Pulse
Width
1.0µs Min.
t
CL
Clock '0' Pulse
Width
1.0µs Min.
t
IR
Clock Rise Time
100ns Typ.
t
IF
Clock Fall Time
100ns Typ.
ENCODER DATA
OUTPUT
t
PCO
DECODER
CLOCK
DECODER TIMING
DATA CLOCKED
t
SU
Data Set-up Time
450ns Min.
t
H
Data Hold Time
600ns Min.
DECODER DATA
INPUT
t
SU
t
SU
+ t
H
Data True
Time.
t
H
DATA TRUE TIME
MULTIPLEXING FUNCTION
ENCODER
OUTPUT
HIGH Z
HIGH Z
t
PCO
Clock to Output
Delay time
750ns Max.
t
DR
Data Rise Time
100ns Typ.
t
DF
Data Fall Time
100ns Typ.
Xtal Input Frequency
1.024MHz.
t
DR
DATA ENABLE
t
DF
Fig.4 Codec Timing Diagrams
Codec Performance ......
Using the Bit Sequence Tests (a to g) at the Decoder Input pin in accordance with
the Eurocom Specification D1 – IA8, the decoder output is as shown in Table 1.
Test
Sample Rate
Bit Sequence at Decoder Input
MLA
Duty cycle
0
0
0.05
0.05
0.1
0.1
0.2
0.2
0.3
0.3
0.4
0.4
0.5
0.5
Typical
Output
Level
- 41.5dBm0
- 42.0dBm0
- 25.0dBm0
- 25.0dBm0
- 19.0dBm0
- 18.5dBm0
- 11.0dBm0
- 11.5dBm0
- 6.5dBm0
- 6.5dBm0
- 3.0dBm0
- 3.0dBm0
0dBm0
0dBm0
a.
b.
c.
d.
e.
f.
g.
16kbit/s
32kbit/s
16kbit/s
32kbits
16kbits
32kbit/s
16kbit/s
32kbit/s
16kbit/s
32kbit/s
16kbit/s
32kbit/s
16kbit/s
32kbit/s
10110100100100101101
1011011010101001001001001001010101101101
11011001001001001101
1011011010101001001000100100101011011011
10110101000100101011
1101101101010010001000100100101011011101
11011001000010011011
1101110110010100010000100010011010111011
11011010000010010111
1110111011001000100000010001001101110111
11011010000001001111
1111011101010001000000001000101011101111
11101010000000101111
1111101110100010000000000100010111011111
Table 1 Bit Sequence Test Table
5
CMLMICRO [ CML MICROCIRCUITS ]
