Application Information ......
Decoder Timing
CHIP SELECT
tCSE
tCYC
tCSH
SERIAL CLOCK
tPWL
tPWH
tDE
tCDS
tDH
tHIZ
DATA OUT
BIT 0
BIT 5
BIT 4
TRI-STATE
tIR
IRQ
Fig.4 Data-Read Timing
Decoder Timing Characteristics
With reference to Figure 4, Data-Read Timing.
Characteristics
Min.
Typ.
Max.
Unit
tPWH
tPWL
tCYC
tCSE
tCSH
tDH
tCDS
tIR
tDE
Serial Clock “High” Pulse Width
Serial Clock “Low” Pulse Width
Serial Clock-Cycle Time
Chip Select Low to Clock “High” Edge
Last Clock “High” Edge to CS “High”
Data Out Hold Time
Clock Edge to Data Out Set Time
Interrupt (IRQ) Reset Time
Chip Select “Low” to Data Enable
Chip Select “High” to Output Tri-State
250
250
600
450
600
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
200
200
200
1000
tHIZ
-
Notes
1 Data is output bit 5 first. Bit 5 can be clocked into the µProcessor by the first Serial Clock rising edge.
If 8 Serial Clock pulses are employed the last 2 data-bits will be “0” and should be ignored by the
software.
2 Chip Select should be used to react to Interrupts and then returned to a logic “1”.
If Chip Select stays low there will be no further Interrupts and no Data Output update.
6
CMLMICRO [ CML MICROCIRCUITS ]
