Baseband Processor For Mixed Mode Land Mobile Radio
CMX880
$B2 RSSI THRESHOLDS: 16-bit write-only
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
High Threshold [Range: 0 to 255]
Low Threshold [Range: 0 to 255]
If the RSSI level exceeds the High Threshold, the ‘RSSI Present’ bit of the ‘STATUS’ register will be set to 1. If
the RSSI level falls below the Low Threshold, the ‘RSSI Absent’ bit of the ‘STATUS’ register will be set to 1. For
each condition, if the corresponding interrupt bit is enabled, a “C-BUS” interrupt will be generated. These status
bits are cleared when the ‘Status’ register is read. The behaviour of the CMX880 is not defined if the high
threshold is less than the low threshold.
Threshold resolution:
Threshold accuracy:
Differential Linearity:
VDD(A)/256 V per LSB.
±2 LSB.
±1 LSB [monotonic].
The ‘RSSI THRESHOLD’ register must not be updated whilst RSSI monitoring is enabled.
$B3 RSSI TIMING: 8-bit write-only
7
6
5
4
3
2
1
0
Bit:
0
0
Conversion Interval
The ‘Conversion Interval’ defines the time between measurements of the RSSI input level whilst in ‘RSSI Monitor’
mode. This allows the user to trade-off device power consumption with receiver response time.
RSSI Monitor mode power
Conversion Interval resolution
Recommended Maximum
Conversion Interval
= 0.5mW/VDD(A)/conversion
= 12ms/conversion per LSB.
(approximate)
(approximate)
= 120ms
(for auto start-up)
The Recommended Maximum Conversion Interval is recommended for automatic receiver start-up on RSSI level
exceeding the ‘RSSI High Threshold’. The user should set an interval to ensure that none of the start of a
received signal is missed, so that the signal type can be correctly identified.
The ‘RSSI TIMING’ register must not be updated whilst RSSI monitoring is enabled.
$B4 RSSI MEASUREMENT DATA: 8-bit read-only
7
6
5
4
3
2
1
0
Bit:
RSSI Level
This data holds the result of the last RSSI level measurement performed by the auxilliary ADC.
$C0 POWER DOWN AND RSSI MONITORING CONTROL: 16-bit write-only
15
14
13
12
11
10
9
8
Bit:
Bit:
MIC 1
MIC 2
FM Disc
ADC
DAC 1
DAC 2
MOD 1
MOD 2
0
7
6
5
4
0
3
2
1
Audio Op
BIAS
Signal
Processor
Xtal_N
Clock_Out_N
EN RSSI
Monitor
RSSI Auto
start-up
Bits 15-5 provide the power control of the specified blocks. If a bit is 1, the corresponding block is on, else it is
powered down. Bits 4 is reserved; set to 0. Bit 5 resets the internal signal processing block and places it into
power-save mode. The clock output is disabled by setting ‘Clock_Out_N’ (bit 2) to ‘1’. On reset, bit 2 is cleared
to ‘0’, so that clock output is enabled.
ã 2001 Consumer Microcircuits Limited
45
D/880/1
CMLMICRO [ CML MICROCIRCUITS ]
