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CMX880D6 参数 Datasheet PDF下载

CMX880D6图片预览
型号: CMX880D6
PDF下载: 下载PDF文件 查看货源
内容描述: [RF and Baseband Circuit, PDSO28, SSOP-28]
分类和应用: 电信光电二极管电信集成电路
文件页数/大小: 80 页 / 748 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Baseband Processor For Mixed Mode Land Mobile Radio  
CMX880  
Table 16 Gain, Path Selection And Power Save Options  
Input Selection  
1. All inputs off (power-saved).  
2. MIC_1 (all other inputs power-saved).  
3. MIC_2 (all other inputs power-saved).  
4. FM_DISC (all other inputs power-saved).  
Delta-Sigma ADC Control  
Delta-Sigma DAC Control  
1. Enable ADC (power saved when disabled).  
2. ADC input gain.  
1. Enable DAC (power-saved when disabled).  
Output Amplifier Controls and  
Selection  
1. Enable Audio output (power-saved when disabled) + gain control.  
2. Enable MOD_1 output (power-saved when disabled) + gain control.  
3. Enable MOD_2 output (power-saved when disabled) + gain control.  
4. Set up ramp rate for switching between outputs or starting/ending  
transmissions.  
MOD_1 and MOD_2 outputs can be selected individually or both together.  
Audio and modulator outputs cannot be selected at the same time, so if  
the Audio output is enabled, the output is routed to it, irrespective of the  
Modulator selection state. Thus to minimise power, the Modulators  
should be disabled by the user when the Audio output is enabled.  
Before switching from Modulator to Audio output, or powering down the  
Modulator outputs, the Modulator signal is ramped to VBIAS  
Before switching from Audio output to Modulator output, the Audio output  
level is ramped to VBIAS  
.
.
Before the Audio output is powered down, the Audio output level is  
ramped down to VBIAS to avoid audible transient noise. On power down,  
the outputs become high impedance (floating).  
Signal Processing (SP) Block  
Control  
The power save should only occur when the SP Block has reached a  
suitable stage in whatever operation it might be performing, so disabling  
of the clock must wait until the SP Block signals that it is in a quiescent  
state. No data or register status will be lost by disabling the clock. If the  
ADC and DAC are both in power-save mode, the SP Block will have  
nothing to do and can therefore be placed in power-save mode by  
disabling its local clock source.  
Input Signal Destination  
Output Signal Source  
TEST ONLY MODES  
1. OFF.  
2. Digitised signal data to “C-BUS”.  
3. Digitised signal data to FSB.  
4. Digitised signal data to output signal path..  
1. OFF.  
2. Digitised signal data from “C-BUS”.  
3. Digitised signal data from FSB.  
4. Digitised signal data from input signal path.  
RESERVED MODES NOT AVAILABLE FOR CUSTOMER USE  
ã 2001 Consumer Microcircuits Limited  
38  
D/880/1  
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