Low Power V.32 bis Modem
CMX869
Status Register bits 6-0: All Rx Modem modes
IRQ
Mask bit
b6
b5
b4
b3
Set to 1 on Rx data ready. Cleared by read from Rx Data Register
Set to 1 on Rx data overflow. Cleared by read from Rx Data Register
Set to 1 on Rx UART framing error
Start-Stop mode: set to 1 if Rx character has even parity (first character if
in 2-character mode)
b0
b0
-
-
b2
Start-Stop mode: 1 if second Rx character has even parity (2-character
mode)
-
b1
b0
Set to 1 if Rx Data Register contains 2 characters (2-character mode)
FSK frequency demodulator output (0 in QAM modes)
-
-
Notes: The IRQ Mask Bit column shows the corresponding IRQ Mask bits in the General Control
Register. A 0 to 1 transition on any of the Status Register bits 14-5 will cause the IRQ bit 15 to be
set to 1 if the corresponding IRQ Mask bit is 1. The IRQ bit is cleared by a read of the Status
Register or a General Reset command or by setting b7 or b8 of the General Control Register to 1.
The IRQN output pin will be pulled low (to VSS) when the IRQ bit of the Status Register and the
IRQNEN bit (b6) of the General Control Register are both set to 1.
The operation of the FSK data demodulator and pattern detector circuits within the CMX869 do not
depend on the state of the Rx energy detect function.
Figure 9a Operation of Status Register bits 5-10
Changes to Status Register bits caused by a change of Tx or Rx operating mode can take up to
150µs to take effect.
The Ring Detect bit (b14) continues to operate in Powersave mode or when the Reset bit (b7) of
the General Control Register is 1. The Ring Detect bit follows the inverted state of the RDN input
pin. An interrupt is only generated as a result of a negative transition on the RDN pin, if General
Control Register bits 5 and 6 are set to 1.
In Rx FSK modem modes bit 0 will show the output of the frequency demodulator, updated at 8
times the nominal data rate.
© 2004 CML Microsystems Plc
31
D/869/4
CMLMICRO [ CML MICROCIRCUITS ]
