Low Power V.22 bis Modem
CMX868
of a Stop bit are then checked and the data bits in the Rx Data Buffer copied to the C-BUS Rx Data
Register.
Figure 8a Rx Modem Data Paths
Whenever a new character is copied into the C-BUS Rx Data Register, the Rx Data Ready flag bit of the
Status Register is set to ‘1’ to prompt the µC to read the new data and, in Start-Stop mode, the Even Rx
Parity flag bit of the Status Register is updated.
In Start-Stop mode, if the Stop bit is missing (received as a ‘0’ instead of a ‘1’) the received character will
still be placed into the Rx Data Register and the Rx Data Ready flag bit set, but, unless allowed by the
V.14 overspeed option described below, the Status Register Rx Framing Error bit will also be set to ‘1’
and the USART will re-synchronise onto the next ‘1’ – ‘0’ (Stop – Start) transition. The Rx Framing Error
bit will remain set until the next character has been received.
Figure 8b Rx USART Function (Start-Stop mode, 8 Data Bits + Parity)
If the µC has not read the previous data from the Rx Data Register by the time that new data is copied to
it from the Rx Data Buffer then the Rx Data Overflow flag bit of the Status Register will be set to 1.
The Rx Data Ready flag and Rx Data Overflow bits are cleared to 0 when the Rx Data Register is read
by the µC.
For QAM and DPSK Start-Stop modes, V.14 requires that the receive USART be able to cope with
missing Stop bits; up to 1 missing Stop bit in every 8 consecutive received characters being allowed for
the +1% overspeed (basic signalling rate) V.14 mode and 1 in 4 for the +2.3% overspeed (extended
signalling rate) mode.
To accommodate the requirements of V.14, the CMX868 Rx Mode Register can be set for 0, +1% or
+2.3% overspeed operation in QAM or DPSK Start-Stop modes. Missing Stop bits beyond those allowed
by the selected overspeed option will set the Rx Framing Error flag bit of the Status Register.
ã 2004 CML Microsystems Plc
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D/868/9
CMLMICRO [ CML MICROCIRCUITS ]
